Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
1998-11-16
2001-01-30
Jean Pierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C375S238000
Reexamination Certificate
active
06181266
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a Digital-to-Analog (D/A) conversion and more particularly, to a D/A conversion method and a D/A converter designed for this method, in which Pulse Width Modulation (PWM) is used.
2. Description of the Prior Art
FIG. 1
schematically shows a conventional D/A converter, which is comprised of a Pulse Width Modulator (PWM) circuit
102
, a latch circuit
104
, and a Low-Pass Filter (LPF) circuit
105
.
A digital input signal S
IN
is applied to the PWM circuit
102
. The input signal S
IN
is a stream of coding pulses produced by modulating or encoding an original analog input signal according to Pulse Code Modulation (PCM). In other words, the input signal S
In
is a stream of Pulse-Code-Modulated (PCM) pulses.
The PWM circuit
102
receives the digital input signal S
IN
through an input terminal T
1
. The PWM circuit
102
modulates the PCM input signal S
IN
to produce a modulated output signal S
PWM
having a variable pulse width proportional to the amplitude of the input signal S
IN
. The modulated output signal S
PWM
is applied to the latch circuit
104
.
The latch circuit
104
is formed by a Complementary Metal-Oxide-Semiconductor (CMOS) inverter comprising p- and n-channel MOS Field_effect Transistors (MOSFETs) M
1
and M
2
. Gates of the MOSFETs M
1
and M
2
are coupled together to be connected to the output terminal of the PWM circuit
102
. A source of the n-channel MOSFET M
2
is connected to the ground. A source of the p-channel MOSFET M
1
is connected to a power supply line applied with a power supply voltage V
SS
. Drains of the MOSFETs M
1
and M
2
are coupled together to be connected to an input terminal of the LPF circuit
105
.
When the PWM output signal S
PWM
is in the logic high (H) level, the modulated output signal S
LC
of the latch circuit
104
is in the logic low (L) level. Thus, the output signal S
LC
is equal to zero or the ground voltage. When the PWM output signal S
PWM
is i the logic L level, the output signal S
LC
of the latch circuit
104
is in the logic H level. Thus, the output signal S
LC
is equal to the power supply voltage V
SS
.
The LPF circuit
105
receives the output signal S
LC
of the latch circuit
104
and removes its high-frequency components, thereby producing a smooth continuous analog output signal S
OUT
at an output terminal T
2
. The analog output signal S
OUT
is a same as the original analog input signal.
With the conventional D/A converter described above, when the maximum pulse width of each sample of the input signal S
IN
is W
S
, the sampling frequency is f
S
, and the pulse voltage of each sample is V
P
, the maximum voltage V
MOUT
of the analog output signal S
OUT
is given as
V
MOUT
=k×W
S
×V
P
, (1)
where k is a constant.
Therefore, to increase the maximum voltage V
MOUT
of the analog output signal S
OUT
, the pulse voltage V
P
of each sample needs to be increased.
Also, when the PCM input signal S
IN
is an n-bit signal (n is a natural number) and the PWM circuit
102
is formed by a counter operated at a frequency f
c
, the clock frequency f
c
of the counter is expressed as
f
c
=f
S
×2
n
(2)
This means that the clock frequency f
c
of the counter needs to be 2
n
times as large as the sampling frequency f
S
. In this case, the magnitude M
QS
of the quantization step of each sample is given as
M
QS
=k×W
S
×V
P
×(
f
S
/f
c
) (3)
Thus, if the clock frequency f
c
of the counter is fixed and the sampling frequency f
S
is unchanged, the maximum voltage V
MOUT
of the analog output signal S
OUT
increases with the increasing voltage V
P
. In this case, however, there arises a disadvantage that the magnitude M
QS
of the quantization step of each sample also becomes larger with the increasing pulse voltage V
P
.
Moreover, if the original analog signal has the highest frequency f
0
, the highest frequency f
0
satisfies the following relationship due to the sampling theorem.
2f
0
≦f
S
(4)
Therefore, from the above equation (2) and the above inequality (4), the clock frequency f
c
of the counter satisfies the following inequality (5).
2×
f
0
×2
n
≦f
c
(5)
It is seen from the inequality (5) that the clock frequency f
c
of the counter has the minimum value of (2×f
0
×2
n
). Accordingly, there arises a disadvantage that the latch circuit
104
serving as an output circuit is required to have a switching speed corresponding to the clock signal with a frequency as high as (2×f
0
×2
n
) or higher.
Additionally, the signal-to-noise ratio (S/N) for a linear- or uniform-quantized PCM signal is given by
S/N=
1.7+6
B,
(6)
where B is the number of quantization bits of the PCM signal. Therefore, the S/N of the PCM signal degrades with its decreasing level due to quantization noise. If the number B of the quantization bits is increased to improve the S/N, the total amount of information to be transmitted is increased.
Thus, to improve the S/N of the PCM signal without increasing the total amount of information to be transmitted, there have been developed and practically used the logarithmic compression codes termed “&mgr;-law” and “A-law”.
The logarithmic compression code “&mgr;-law” is a 8-bit PCM code having first to eighth bits. The full-scale amplitude of the original analog signal is divided into 15 equal segments to form 16 steps. Each of the segments thus formed is linear- or uniform-quantized to form 16 equal quantization steps. The first bit, i.e., the Most Significant Bit (MSB), of the &mgr;-law code is a sign bit to represent the polarity of the original analog signal. The second to fourth bits of the &mgr;-law code are segment bits to designate one of the 16 segments. The fifth to eighth bits of the &mgr;-law code are step bits to designate one of the 16 quantization steps for a corresponding one of the 16 segments.
The logarithmic compression code “A-law” also is a 8-bit PCM code having first to eighth bits. The full-scale amplitude of the original analog signal is divided into 13 equal segments to form 14 steps. Each of the segments thus formed is linear- or uniform-quantized to form 16 equal quantization steps. The first bit, i.e., the Most Significant Bit (MSB), of the A-law code is a sign bit to represent the polarity of the original analog signal. The second to fourth bits of the A-law code are segment bits to designate one of the 14 segments. The fifth to eighth bits of the A-law code are step bits to designate one of the 16 quantization steps for a corresponding one of the 14 segments.
With the conventional D/A converter shown in
FIG. 1
, however, there are the following problems.
First, the maximum pulse width of the PWM signal S
PWM
is determined by the sampling frequency f
S
. Therefore, to improve the pulse-width resolution of the PWM signal S
PWM
, the clock frequency f
c
of the counter serving as the PWM circuit
102
, which determines the step number of the variable pulse width of the PWM signal S
PWM
, needs to be raised. In this case, however, there arises a problem that the relating hardware is required to operate at a higher speed and the power consumption is increased.
If the voltage or amplitude of the PWM signal S
PWM
is increased in order to expand the dynamic range of the analog output signal S
OUT
, the quantization step is increased and as a result, the minimum level of the output signal S
OUT
becomes higher according to the increased quantization step. Therefore, in this case also, the clock frequency f
c
of the counter serving as the SWM circuit
102
needs to be raised for reduction of the quantization step. Thus, there arises the same problem as above.
Second, there is a problem that the highest switching speed of the latch circuit
104
, which allows the clock frequency f
c
of the counter having the minimum value of (2×f
o
×2
n
) to be inputted, limits the highest frequency f
o
Jean Pierre Peguy
NEC Corporation
Young & Thompson
LandOfFree
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