D/A conversion circuit and semiconductor device

Details D/A conversion circuit and semiconductor device D/A conversion circuit and semiconductor device

1998-11-23

2002-08-27

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

With particular solid state devices

C341S145000, C257S351000

Reexamination Certificate

active

06441758

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a D/A conversion circuit for converting a digital signal into an analog signal, and particularly, to a D/A conversion circuit used in a driving circuit of a semiconductor display device.
2. Description of the Related Art
In recent years, a technique for manufacturing a semiconductor device in which a semiconductor thin film is formed on an inexpensive glass substrate, such as a thin film transistor (TFT), has been rapidly developed. The reason is that a demand for an active matrix type semiconductor display device (particularly, an active matrix type liquid crystal display device) has been increased.
The active matrix type liquid crystal display device is structured such that a TFT is disposed for each of several tens to several millions of pixel regions disposed in matrix, and an electric charge going in and out of respective pixel electrodes is controlled by the switching function of the TFT.
Among them, with the improvement of fineness and picture quality of a display device, attention comes to be paid to a digital driving system active matrix type liquid crystal display device capable of being driven at high speed.
FIG. 31
shows a conventional digital driving system active matrix type liquid crystal display device. As shown in
FIG. 31
, the conventional digital driving system active matrix type liquid crystal display device includes a source signal line side shift register
01
, address lines
02
of a digital decoder, latch circuits
03
(LAT1), latch circuits
04
(LAT2), a latch pulse line
05
, D/A conversion circuits (digital/analog conversion circuits)
06
, source signal lines
07
, a gate signal line side shift register
08
, gate signal lines (scanning lines)
09
, pixel TFTs
10
, and the like. Here, the 2-bit digital driving system active matrix type liquid crystal display device is taken for instance. Incidentally, in the latch circuits LAT1 and LAT2, respectively, two latch circuits are shown in one bundle for convenience.
Digital gradation signals supplied to address lines
02
(1 and 2) of the digital decoder are written in the LAT1 group by timing signals from the source signal line side shift register
01
.
A time in which writing of the digital gradation signals into the LAT1 group is roughly completed, is referred to as one line period. That is, one line period is a time interval between the start point of writing of a gradation signal from the digital decoder into the leftmost LAT1 and the end point of writing of a gradation signal from the digital decoder into the rightmost LAT1.
After the writing of the gradation signals into the LAT1 group is completed, when a latch pulse flows to the latch pulse line
05
synchronously with the operation timing of the shift register, the gradation signals written in the latch
1
group are transmitted all at once into the LAT2 group and are written.
Into the LAT1 group which have finished transmission of the gradation signals into the LAT2 group, writing of gradation signals supplied to the digital decoder is again sequentially carried out by a signal from the source signal line side shift register
01
.
In the second one line period, according to the gradation signals transmitted to the LAT2 group synchronously with the start of the second one line period, one of four gradation voltages is selected by the D/A conversion circuits
06
.
The selected gradation voltage is supplied to the corresponding source signal line in one line period.
By repeating the above-mentioned operation, images are supplied to the entire pixel portion of the liquid crystal display device.
Here, the conventional D/A conversion circuit used in the foregoing driving circuit will be described.
FIG. 32
shows the D/A conversion circuit
06
of the foregoing active matrix type liquid crystal display device. As shown in
FIG. 32
, the D/A conversion circuit
06
is made up of four NAND circuits 22.1 to 22.4, four gradation voltage lines (V0 to V3) 23, and four P-channel TFTs 24.1 to 24.4.
Such a structure is adopted that one of the four P-channel TFTs 24.1 to 24.4 is selected according to signals supplied from the LAT2 group to signal lines
21
a
and
21
b
and their inversion signals. Then a voltage is applied to the source signal line
07
from the gradation voltage line connected to the selected TFT.
A circuit pattern diagram and a circuit diagram of the NAND circuit
22
of the above D/A conversion circuit
06
are shown in
FIGS. 33A and 33B
, respectively. In
FIG. 33A
, wiring lines having the same pattern indicate the same wiring layers. Reference numerals
33
,
34
and
38
denote gate electrode wiring layers, and
35
to
37
denote second wiring layers formed over the gate electrode wiring layers with an insulating layer interposed therebetween.
Reference numeral
31
denotes a semiconductor active layer of a P-channel TFT, and
32
denotes a semiconductor active layer of an N-channel TFT. Reference numerals
33
and
34
denote gate electrode wiring lines, and form TFTs Tr1 and Tr4, and TFTs Tr2 and Tr3, respectively. An input signal Vin1 is inputted to the gate electrode wiring line
34
, and an input signal Vin2 is inputted to the gate electrode wiring line
33
. Reference numeral
35
denotes a wiring line for supplying a voltage from Vdd, which is connected to source regions of the TFTs Tr1 and Tr2. The second wiring layer
36
is connected to drain regions of the TFTs Tr1 and Tr2 and a drain region of the TFT Tr3, and supplies an output signal to the gate electrode wiring layer
38
Vout. The second wiring layer
37
denotes a GND wiring line, and is connected to a source region of the TFT Tr4. Blackened portions
39
indicate portions where the semiconductor active layer is connected to the second wiring layer, or the gate electrode wiring layer is connected to the second wiring layer.
FIG. 33B
shows an equivalent circuit of the circuit pattern of the NAND circuit of the D/A conversion circuit shown in FIG.
33
A.
According to
FIGS. 33A and 33B
, in the NAND circuit, there are many (five) portions (typically denoted by reference numeral
40
) where the second wiring layer is connected to the semiconductor active layer or the gate electrode wiring layer. In these connection portions, in order to compensate a shift which occurs at the time of making a contact hole for the above connection, the semiconductor active layer must be made large more than needs. Thus, there is a defect that the whole area of the circuit becomes large.
In the foregoing 2-bit D/A conversion circuit, four such NAND circuits are required. Moreover, in the whole driving circuit, the number of required D/A conversion circuits is equal to the number of source signal lines. As a result, the rate of the area of the D/A conversion circuits (NAND circuits) occupying the driving circuit becomes large. This is one of causes of hindering the miniaturization of a semiconductor display device.
In order to improve the fineness of the semiconductor display device, it becomes necessary to increase the number of pixels, that is, the number of source signal lines. However, as described above, one D/A conversion circuit is necessary for one signal line, which is one of causes of hindering the improvement in the fineness.
FIG. 34
shows another conventional digital driving system active matrix type liquid crystal display device. As shown in
FIG. 34
, the conventional digital driving system active matrix type liquid crystal display device includes a source signal line side shift register
51
, address lines (a to d)
52
of a digital decoder, latch circuits (LAT1)
53
, latch circuits (LAT2)
54
, a latch pulse line
55
, D/A conversion circuits
56
, gradation voltage lines
57
, source signal lines
58
, a gate signal line side shift register
59
, gate signal lines (scanning lines)
60
, pixel TFTs
61
, and the like. Here, the 4-bit digital driving system active matrix type liquid crystal display device is taken for instance. Incidentally, in the latch circuits LAT1 and LAT2, respe

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