D/A conversion circuit and semiconductor device

Details D/A conversion circuit and semiconductor device D/A conversion circuit and semiconductor device

2000-08-14

2002-03-12

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C345S098000

Reexamination Certificate

active

06356223

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a D/A conversion (digital/analog conversion) circuit, and more particularly, to a D/A conversion circuit to be used in a driver circuit of a semiconductor device.
It should be noted that in this specification, the term “semiconductor device” is intended to generally indicate all of such an apparatus capable of operating by employing semiconductor properties. For example, the semiconductor device can include an electro-optical device, a semiconductor circuit, or an electronic equipment.
2. Description of the Related Art
In recent years, the technique for manufacturing a semiconductor device, e.g., a thin film transistor (TFT), in which a semiconductor thin film is formed on an inexpensive glass substrate shows rapid advancement because of increased demand for an active matrix type semiconductor display device (in particular, an active matrix type liquid crystal display device).
The active matrix type liquid crystal display device includes several hundred thousands to several millions of pixel regions arranged in matrix. Each of the pixel regions is provided with a TFT which controls, through its switching function, electric charges to be supplied to or discharged from a corresponding pixel electrode.
Specifically, with high finer processing and higher image quality of a display device being required, an active matrix type liquid crystal display device of digital driving type capable of operating at a higher speed has drawn much attention.
FIG. 19
shows a conventional active matrix type liquid crystal display device of digital driving type. This conventional active matrix type liquid crystal display device of digital driving type is composed of, as shown in
FIG. 19
, such components as a source signal line shift register
1401
, digital decoder address lines (a-d)
1402
, latch circuits (LAT
1
)
1403
, other latch circuits (LAT
2
)
1404
, a latch pulse line
1405
, D/A conversion circuits
1406
, gradation (gray scale) voltage lines
1407
, source signal lines
1408
, agate signal line shift register
1409
, gate signal lines (scanning lines)
1410
, and pixel TFTs
1411
. Herein, a 4-bit active matrix type liquid crystal display device of digital driving type is taken as an example. It should be noted that for simplicity, each of the illustrated latch circuits (LAT
1
and LAT
2
) in
FIG. 19
actually represents four of the latch circuits.
Digital signals (digital gradation signals) supplied to the address lines (a-d)
1402
of the digital decoder are sequentially written onto groups of the latch circuits LAT
1
(LAT
1
groups) in accordance with timing signals supplied from the source signal line shift resister
1401
.
A time period required until completion of a set of writing operations of the digital signals for the LAT
1
groups is referred to as “one line period”. More specifically, the one line period corresponds to a time period from the time when the writing operation of the digital signal from the digital decoder to the most leftward LAT
1
is started until the time when the writing operation of the digital signal from the digital decoder to the most rightward LAT
1
is completed.
After the completion of writing operations of the digital signals for the LAT
1
groups, the digital signals thus written into the LAT
1
groups are simultaneously transmitted to and written onto the LAT
2
groups at the time when a latch pulse appears on the latch pulse line in accordance with the operation timings of the shift register.
Onto the LAT
1
groups that have thus transmitted the digital signals to the LAT
2
groups, other digital signals supplied to the digital decoder are again written sequentially in accordance with the signals supplied from the source signal line shift register.
During this second-round one line period, voltages in accordance with the digital signals transmitted to the LAT
2
groups are supplied to the source signal lines in synchronization with the start of the second-turn one line period. In the exemplary driver circuit described herein, conversion of the digital signals into gradation voltages is implemented by selecting one of the 16 gradation voltage lines by means of the D/A conversion circuit.
The selected gradation voltage is supplied to the corresponding source signal line during the one line period. The corresponding TFT is switched in response to a scanning signal from the gate signal line shift register so that liquid crystal molecules are driven.
By repeating the above-mentioned operations for the number of the scanning lines, one picture (one frame) is created. In general, in the active matrix type liquid crystal display device,
60
frames of images are switched per second.
With reference to
FIG. 20
, a conventional D/A conversion circuit to be used in the above-mentioned digital driver circuit will be described below.
The conventional 4-bit D/A conversion circuit comprises a plurality of switches (sw
0
-sw
15
) and a plurality of gradation voltage lines (V
0
-V
15
). One of the switches (sw
0
-sw
15
) is selected in accordance with the 4-bit digital signal supplied from the LAT
2
groups, and a voltage is supplied to the source signal line
1407
from the gradation voltage line coupled to the selected switch.
One D/A conversion circuit as described above is provided substantially to each of the source signal lines.
The conventional 4-bit D/A conversion circuit as set forth above includes the 16 switches and the 16 gradation voltage lines. Furthermore, the number of the switches will be required to increase in an exponential manner with an increase in the number of bits. In other words, the conventional D/A conversion circuit intended to handle n-bit digital signal requires 2
n
switches. Accordingly, in an actual active matrix type liquid crystal display device, a large area is occupied by the switches, resulting in a large area occupied by the whole driver circuit. This is disadvantageous for realizing miniaturization of the device.
With reference to
FIG. 21
, another conventional D/A conversion circuit to be used in the above-mentioned digital driver circuit will be described below. In the 4-bit D/A conversion circuit as shown in
FIG. 21
, similarly to the 4-bit D/A conversion circuit as described above, one of the switches (sw
0
-sw
15
) is selected in accordance with the 4-bit digital signal supplied from the LAT
2
groups, and a voltage is supplied to the source signal line from the gradation voltage line coupled to the selected switch.
The D/A conversion circuit shown in
FIG. 21
includes five gradation voltage lines (V
0
-V
4
), and the number of the line is less than that of the 4-bit D/A conversion circuit in
FIG. 20
as described above.
The voltage to be applied across the V
0
to V
4
is divided by way of resistors so that voltages of different levels are supplied to the respective five gradation voltage lines (V
0
-V
4
). In particular, the highest voltage is applied to the V
4
, while the lowest voltage is applied to the V
0
.
However, the D/A conversion circuit shown in
FIG. 21
has a problem in which the overall resistance becomes large because the voltages to be applied to the respective gradation voltage lines are divided via the resistors, whereby a sufficient writing time of display data to a liquid crystal panel cannot be obtained.
In addition, when the number of bits increases, a device resistance and wiring resistance also increase.
Furthermore, in order to realize high finer definition of a semiconductor display device, the number of pixels, i.e., the number of source signal lines, are required to be increased.
Moreover, as described previously, an increase in the number of source signal lines leads to an increase in the area occupied by the D/A conversion circuit, as well as increases in the wiring remittances and the device resistance. These will also prevent high finer definition from being realized.
SUMMARY OF THE INVENTION
In view of the disadvantages as described above, an object of the present invention is to provide

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