D/A conversion apparatus

Details D/A conversion apparatus D/A conversion apparatus

1999-03-11

2001-10-09

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S143000

Reexamination Certificate

active

06300891

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital to analog (D/A) conversion apparatus for converting a digital signal to an analog signal, and more particularly to an oversampling D/A conversion apparatus which performs D/A conversion using a sampling frequency higher than the sampling frequency of the digital input signal.
2. Description of the Related Art
Among D/A converters, a D/A conversion apparatus is known that utilizes a noise shaper and a 1-bit D/A converter array. A prior known D/A conversion apparatus of this type will be described with reference to FIG.
6
. Techniques involved in this apparatus are disclosed in the following literature A and B.
Literature A: Japanese Patent Unexamined Publication No. 5-335963
Literature B: Technical Report of IEICE, CAS94-9
FIG. 6
is a block diagram showing one example of the prior known D/A conversion apparatus. In
FIG. 6
, a digital filter
10
is provided to increase the sampling frequency f
s
of the input digital signal, for example, the digital audio signal reproduced from a compact disc, by a factor of k (k is an integer). For purposes of explanation, it is assumed here k=64.
A noise shaper
11
is used for quantizing (word length limiting) the digital output signal of the digital filter
10
, and for changing the frequency characteristic of noise in a controlled manner. More specifically, in this case, the frequency characteristic is changed, for example, in such a manner as to reduce the noise level at low frequencies while increasing the noise level at high frequencies. A noise shaper with a second-order characteristic is used here, its output Y for input X being expressed by equation (1) below.
Y=X+
(1
−z
−1
)·
V
q
  (Equation 1)
where
V
q
: Quantization error
z
−1
: cos &thgr;−j·sin &thgr;
j: Imaginary unit
The following description assumes that the output Y represents seven (=p) levels (0 to 6).
A pointer
50
outputs a remainder of the accumulated value of the input signal. In this example, the output of the noise shaper
11
is accumulated and a remainder modulo 6 is output. Denoting the input to the pointer
50
at a given time t as X
t
, the output Y
t
is given by equation (2) below.
 
Y
t
=(
X
t−1
+Y
t−1
)mod 6  (Equation 2)
where
X
t−1
: Input one sample back
Y
t−1
: Output one sample back
A ROM (read only memory)
51
outputs 6-bit data in response to an address with the input signal as the low order part and the output of the pointer
50
as the high order part.
A 1-bit D/A converter array
52
consists of six (=n) identical 1-bit D/A converters
521
to
526
, and converts the 6-bit data output from the ROM
51
into analog signals.
An analog adder
14
D sums the six analog signals output from the 1-bit D/A converters
521
to
526
, and outputs the result as an analog signal.
The 1-bit D/A converters
521
to
526
and the analog adder
14
D together constitute a D/A conversion circuit
15
D.
The D/A conversion apparatus of
FIG. 6
employs the so-called oversampling D/A conversion configuration in which the digital filter
10
and noise shaper
11
convert the digital input signal into a signal with seven (=p) levels at a sampling frequency of 64f
s
, then the seven-level signal is converted by the pointer
50
and ROM
51
into six 1-bit signals which are further converted into an analog signal by the D/A conversion circuit
15
D, thus accomplishing the digital to analog conversion with a higher sampling frequency.
FIG. 7
shows the spectrum of the output signal of the D/A conversion apparatus of
FIG. 6
, obtained by computer simulation assuming the use of an ideal D/A conversion circuit
15
D. For simplicity, the signal is shown here in the range of 0 to 2f
s
. Although the analog signal is reconstructed from the digital signal representing only seven levels, as stated above, a dynamic range greater than 90 dB is obtained in the signal band of 0 to f
s
/2, as shown in
FIG. 7
, by virtue of the shifting of the noise frequency characteristic through the noise shaper
11
.
In a practical circuit, however, it is not possible to manufacture the 1-bit D/A converters
521
to
526
all identical in characteristic, but some degree of variation (relative errors) inherently occurs between their outputs, resulting in noise generation. The following describes a method in which the 1-bit D/A converters
521
to
526
are used in a cyclic fashion in order to suppress this noise.
First, the pointer
50
accumulates the seven-level signal (0 to 6) output from the noise shaper
11
of
FIG. 6
, and obtains a remainder modulo 6 for output. The pointer
50
thus presents six possible outputs 0 to 5.
Next, an address consisting of the input signal (the output signal of the noise shaper
11
) as the low order part and the output signal of the pointer
50
as the high order part is supplied to the ROM
51
, and 6-bit data is obtained. The 6-bit data represents six non-weighted 1-bit signals. Table 1 shows the relationship between the address (in decimal notation) and the data (six 1-bit signals) at this time. In Table 1, data
0
is represented by symbol . for easy viewing.
TABLE 1
High
order
Data
Low order = 0
0
. . . . . .
1
. . . . . .
2
. . . . . .
3
. . . . . .
4
. . . . . .
5
. . . . . .
Low order = 1
0
. . . . . 1
1
. . . . 1 .
2
. . . 1 . .
3
. . 1 . . .
4
. 1 . . . .
5
1 . . . . .
Low order = 2
0
. . . . 1 1
1
. . . 1 1 .
2
. . 1 1 . .
3
. 1 1 . . .
4
1 1 . . . .
5
1 . . . . 1
Low order = 3
0
. . . 1 1 1
1
. . 1 1 1 .
2
. 1 1 1 . .
3
1 1 1 . . .
4
1 1 . . . 1
5
1 . . . 1 1
Low order = 4
0
. . 1 1 1 1
1
. 1 1 1 1 .
2
1 1 1 1 . .
3
1 1 1 . . 1
4
1 1 . . 1 1
5
1 . . 1 1 1
Low order = 5
0
. 1 1 1 1 1
1
1 1 1 1 1 .
2
1 1 1 1 . 1
3
1 1 1 . 1 1
4
1 1 . 1 1 1
5
1 . 1 1 1 1
Low order = 6
0
1 1 1 1 1 1
1
1 1 1 1 1 1
2
1 1 1 1 1 1
3
1 1 1 1 1 1
4
1 1 1 1 1 1
5
1 1 1 1 1 1
To describe Table 1, the 6-bit data contains as many is as indicated by the numeric value of the input signal, i.e., the low order part of the address, so that the sum of the bits becomes equal to the input signal. Further, the bits are shifted in a cyclic fashion to the left by the same number of bit positions as indicated by the numeric value of the output signal of the pointer
50
, i.e., the high order part of the address, any overflown bits appearing from the right. When the ROM
51
is defined as shown in Table 1, data is output, for example, as shown in Table 2, for the input data at respective times.
TABLE 2
Input (Low
Output of pointer 30
order part of
(High order part of
Output of ROM 51
Time
address)
address)
(Data)
t
0
1
0
. . . . . 1
t
1
3
1
. . 1 1 1 .
t
2
1
4
. 1 . . . .
t
3
1
5
1 . . . . .
t
4
6
0
1 1 1 1 1 1
t
5
4
0
. . 1 1 1 1
t
6
2
4
1 1 . . . .
t
7
2
0
. . . . 1 1
t
8
6
2
1 1 1 1 1 1
t
9
5
2
1 1 1 1 . 1
t
10
0
1
. . . . . .
t
11
3
1
. . 1 1 1 .
.
.
.
.
.
.
.
.
As can be seen from Table 2, the data is output in such a manner that the same number of 1s as indicated by the numeric value of the input signal are shifted in a cyclic fashion through the 6-bit data. This means that there is no correlation between the numeric value of the input signal and any particular bit in the 6-bit data. This serves to reduce the in-band noise even when there are variations between the outputs of the 1-bit D/A converter array
52
to which the 6-bit data are coupled.
However, the configuration shown in
FIG. 6
requires as many 1-bit D/A converters
521
to
526
as the number of output levels of the noise shaper
11
minus one. Generally, in an oversampling D/A conversion apparatus, a greater dynamic range can be obtained as the number of output levels of the noise shaper increases; therefore, if the dynamic range is to be increased, the number of 1-bit D/A converters must be increased correspondingly, resulting in a corresponding increase in the amount of circuitry.
Further, when configuring the D/A conversion apparatus as a balanced c

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