Cyphering/decyphering performed by an integrated circuit

Cryptography – Communication system using cryptography – Symmetric key cryptography

Reexamination Certificate

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C380S037000

Reexamination Certificate

active

10611254

ABSTRACT:
A method of cyphering and/or decyphering, by an integrated circuit, of a digital input code by means of several keys, comprising: dividing the code into several data blocks of same dimensions; and applying to said blocks several turns of a cyphering or decyphering comprising submitting each block to at least one same non-linear transformation and of subsequently combining each block with a different key at each turn, the operands being masked, upon execution of the method, by at least one first random number having the size of the code and all the blocks of which have the same value by combining, by an XOR-type function, the input and output blocks of the non-linear transformation with said random number.

REFERENCES:
patent: 2003/0223580 (2003-12-01), Snell
patent: 0 981 223 (2000-02-01), None
patent: 1 109 350 (2001-06-01), None
patent: WO 00 41356 (2000-07-01), None
Joan Daemen and Vincent Rijmen, AES Proposal; Rihndael, Mar. 9, 1999, retrieved date Jun. 25, 2006.
Thomas S. Meeserges, Securing the AES Finalists Against Power Analysis Attacks,B. Schneier (Ed) pp. 150-164, 2001□□Retrieved date Jun. 25, 2006.
French Preliminary Search Report from French priority application No. 0208268, filed Jul. 2, 2002.
Akkar, M.L. et al.,An Implementation of DES and AES, Secure Against Some Attacks, Cryptographic Hardware and Embedded Systems, 3rdInternational Workshop, Ches 2001, Paris, France, May 14-16, 2001 Proceedings, Lecture Notes in Computer Science, Berlin: Springer, DE, vol. 2162, 2001 pp. 309-318, XP008002641.
Kocher, P. et al.,Differential Power Analysis, Conference Crypto, 1999, pp. 388-397 XP000279852.

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