Cyclic thermal anneal for dislocation reduction

Details Cyclic thermal anneal for dislocation reduction Cyclic thermal anneal for dislocation reduction

2000-06-23

2003-10-21

Kunemund, Robert (Department: 1765)

Single-crystal, oriented-crystal, and epitaxy growth processes;

Processes of growth from solid or gel state

C117S005000, C117S008000, C117S009000, C117S936000

Reexamination Certificate

active

06635110

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to heteroepitaxial layer processing techniques, and more particularly relates to techniques for improving characteristics of heteroepitaxial layers.
The heteroepitaxial deposition of various III-V and II-VI semiconductors, and particularly germanium (Ge), on silicon (Si) substrates is a research topic of significant technological importance. Successful heteroepitaxial Ge deposition on silicon enables a wide range of optical communication systems and components. A particularly important application is the integration of fast, efficient, low noise Ge photodetectors on Si. Ge photodetectors have the ability to detect light efficiently at the optical communication wavelengths of 1.3 &mgr;m and 1.54 &mgr;m. Integration of Ge detectors with a conventional silicon fabrication process enables production of optical communication systems at the chip level. Specifically, integration of Ge photodetectors on Si with polysilicon waveguide technology enables Si optical interconnect systems. Such a silicon optical interconnect system, or Si microphotonic system, has been suggested by the Semiconductor Industry Association as a means for overcoming metal interconnect limitations. Integration of Ge on Si also has the ability to enhance current MOSFET technology. Because Ge has higher carrier mobility than Si, Ge FET or MOSFET devices fabricated on a silicon substrate provide higher current capability, lower power consumption, lower temperature operation and higher speed than the corresponding silicon devices. Such a Ge FET integrated on a Si substrate can be used in “system on a chip” applications and can enable electronic devices for a wide range of applications. Ge on Si can also replace indium gallium arsenide devices integrated with indium phosphide substrates in the field of near infrared imaging.
The integration of Ge on Si has historically proven to be difficult due to a range of technical challenges. In particular, germanium epi-layers grown on silicon are generally found to suffer from sub-optimal mechanical and electrical characteristics, including high surface roughness due to island formation and high sessile threading dislocation density.
It is generally understood that the formation of Ge islands and the generation of misfit dislocations as a Ge epi-layer is grown on a silicon wafer are due to the 4% lattice mismatch between Ge and Si. Both island formation and misfit dislocation generation are nature's ways of reducing the strain energy associated with the lattice mismatch. Island formation results in large roughness of the top surface of the epitaxial layer. Such surface roughness can obstruct process integration of Ge devices with Si devices, e.g., by disabling accurate photolithographic processes, and by reducing the ability to produce functional multiple metal interconnect layers.
Misfit dislocations are not harmful to semiconductor devices per se because these dislocations are generally constrained to the Ge/Si interface. Misfit dislocations can relax strain between Ge and Si and are beneficial to the stability of the materials system. But the generation of misfit dislocations results in the formation of threading dislocations that connect the misfit dislocations at the Ge/Si interface to the top surface of the Ge epi-layer. Threading dislocations degrade device characteristics, for example, by increasing the leakage current of a rectifying junction and thereby reducing the efficiency of a photodetector. It has accordingly been recognized that both island formation and threading dislocations should be avoided in a Ge epi-layer.
It is well understood that during epitaxial growth of Ge on Si, island formation occurs to relax misfit energy. It has been suggested that by growing Ge on Si at a temperature below about 375° C., island formation could be prevented. Growth of Ge on Si at such a low temperature results in a low film growth rate, however. Growth of a layer of a commercially useful thickness, for example 1 &mgr;m-thick or more, at low temperatures would require a prohibitive process time not commercially feasible as a practical matter.
Reduction of threading dislocations in a Ge epi-layer grown on Si has also been problematic with conventional processing techniques. It has been suggested that threading dislocations in a two-material system of mismatch greater than about 2% cannot be reduced to densities below about 10
9
cm
−2
. Specifically, it has been conventionally understood that in a large-mismatch, two-material system such as Ge—Si, the products of reactions between glissile dislocations in the epi-layer material are sessile dislocations. Once formed, sessile dislocations cannot be removed per se. It has thus been generally understood that the primary technique for growing a high-quality Ge epi-layer on Si with low threading dislocation density is to preserve the glissile dislocation structure by producing an epi layer of relatively low mismatch with the silicon substrate. This has led to efforts at growing relatively thick, e.g., greater than about 12 &mgr;m-thick, graded SiGe buffer layers on Si to produce a high-quality top surface epi-layer region. It has been found, however, that the growth of thick, graded buffer layers results in a high degree of surface roughness that effectively blocks threading dislocation motion, i.e., the dislocations cannot be rendered glissile.
A chemomechanical polishing (CMP) process has been suggested to reduce surface roughness to enable dislocations to glide. Another method proposed to reduce threading dislocation density in highly mismatched two-material systems is a so-called “epitaxial necking” method. This process is based on the fact that sessile dislocations are inclined. Therefore, by growing a thick layer of Ge in small holes on patterned SiO
2
/Si wafers, it is suggested that threading dislocations can be filtered out. For such a process to be enabled, an epi-layer thickness greater than the maximum lateral dimension of the small holes is necessary. Like the “grading” growth method described above, the “epitaxial necking” growth method requires growth of a thick layer of Ge to achieve a high quality Ge layer with low threading dislocation density.
It is well-recognized that thick-layer Ge epi-layer growth techniques like those just described are very difficult to integrate with Si CMOS processing technology due to the much greater thickness of the Ge epi-layer relative to the generally very thin CMOS Si and other microelectronic layers. A variety of techniques have been proposed to ease the integration of Ge on Si by addressing one or the other of the dislocation and surface roughness problems separately. As just discussed, methods for reduction of threading dislocation defects at the top active layer of a thick Ge epi-layer have been proposed, and separately, methods for reducing interface misfit dislocation defects have been developed.
But both the nucleation of interface defects and the reduction and elimination of threading dislocation defects both at the epi-layer top surface and through intermediate regions between the top surface and the epi-substrate interface are required. A Ge epi-layer sufficiently thin to be compatible with Si CMOS integration is, for current conventional growth processes, characterized by an unacceptably high density of threading defects at the top surface as well as regions between top surface and the epi-substrate interface. Lacking a process that addresses all of these requisite materials issues, it has not been commercially feasible as a practical matter to integrate high-quality Ge epi-layers on Si for integration with conventional Si CMOS processes.
SUMMARY OF THE INVENTION
The invention provides processes for producing a very low dislocation density in heterogeneous epitaxial layers with a wide range of thicknesses, including a thickness compatible with conventional silicon CMOS processing.
Specifically, the invention provides a process for reducing dislocation density in a semiconductor material formed as an epitaxial l

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