Cyclic redundancy check synchronizer

Details Cyclic redundancy check synchronizer Cyclic redundancy check synchronizer

1994-09-14

1998-02-03

Elmore, Reba I.

Excavating

371 371, 371 377, G06F 1110, H03M 1300

Patent

active

057152594

ABSTRACT:
A cyclic redundancy check synchronizer includes an N-byte shift register for shifting an input byte string by N bytes and N-1 bytes, a compensation polynomial driver for driving a compensation polynomial by modulo-2-dividing bits of a byte output from the Nth stage of the N-byte shift register by a generator polynomial and shifting the resultant remainder by one bit in a direction toward higher-order bits, and a calculator for inputting bits of an output byte from a remainder register as high-order bits and bits of an input data byte as low-order bits and for performing compensation polynomial modulo-2 subtraction and generator polynomial modulo-2 division for the inputted bits. The cyclic redundancy check synchronizer also includes a block synchronization identifier for searching for syndrome output signals from the calculator at an interval of a byte time to check whether the same syndrome signal is outputted from the calculator successively a predetermined number of times or more at an interval of a block period, and a data selector for selecting bits constituting a byte from among output bits from the N-byte shift register according to a certain one of the syndrome output signals from the calculator resulting in a block synchronous state in response to a data selection signal from the block synchronization identifier to output byte-synchronized data.

REFERENCES:
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patent: 5103451 (1992-04-01), Fossey
patent: 5109385 (1992-04-01), Karp et al.
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patent: 5282214 (1994-01-01), Dravida
patent: 5282215 (1994-01-01), Hyodo et al.
patent: 5325372 (1994-06-01), Ish-Shalom
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Pei, Tong-Bi, et al; High-Speed Parallel CRC Circuits in VLSI; IEEE Transactions on Communications, vol. 40, Apr. 1992.

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