Cyclic redundancy check circuit

Details Cyclic redundancy check circuit Cyclic redundancy check circuit

1992-03-06

1992-11-17

Canney, Vincent P.

Excavating

371 251, G06F 1112

Patent

active

051649438

ABSTRACT:
A media access controller is provided by the present invention. A feature of the media access controller of the present invention is a content addressable memory architecture whereby address filtering is provided for filtering physical, group and broadcast addresses on an Ethernet network. Another feature of the present invention is an interface architecture capable of supporting external address filters which in turn are capable of supporting spanning tree and source routing algorithms. Still another feature of the present invention is a CRC checker having improved testability such that burdensome computations for input bit test patterns are no longer required. Still another feature of the present invention is a first-in, first-out memory register having validity bits associated with each stored data byte, such that data bytes may be indiscriminately stored, regardless of their validity, and invalid data bytes are discarded during retrieval of the stored data bytes.

REFERENCES:
patent: 4809273 (1989-02-01), Jackowski et al.
patent: 5062111 (1991-10-01), Gotou et al.
"The Great CRC Mystery", by Terry Ritter, (Dr. Dobb's Journal, Feb. 1986, pp. 26-34).
"Calculating CRCs By Bits and Bytes", by Greg Morse, (Byte Magazine, Sep. 1986, pp. 115-124).
"The Ethernet: A Local Area Network--Data Link Layer and Physical Layer Specifications", published by Digital Equipment Corp., Intel Corp. and Xerox Corp., Appendix C (Sep. 30, 1980).

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