Cyclic noise reducing apparatus

Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry

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358 36, H04N 5213

Patent

active

048413666

ABSTRACT:
A cyclic noise reducing apparatus for reducing noise in video signals by positively feeding back an output video signal which has been delayed through a field memory circuit for storing and selectively delaying video signals by a field (n lines) or by a field plus one line (n+1 lines) and cyclically adding the output video signal to an input video signal. The delay time is selected using a delay time switch for switching during a vertical scanning period the delay time of the signal positively fed back alternately between n and n+1 line periods. Also, the video signal may be alternately delayed by n or n+1 lines by suspending the writing and reading of data to and from the field memory circuit for one line period during the vertical blanking period of each frame.

REFERENCES:
patent: 4291333 (1981-09-01), Warnock
patent: 4434438 (1984-02-01), Rzeszewski

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