Cyclic digital filter

Details Cyclic digital filter Cyclic digital filter

1993-08-23

1995-01-10

Malzahn, David H.

Boots, shoes, and leggings

G06F 1531

Patent

active

053813588

ABSTRACT:
Disclosed is a cyclic digital filter comprising a feedback loop including a first unit time delay circuit for delaying an input signal by a unit time; a coefficient multiplier for multiplying by a predetermined coefficient the output from the first unit time delay circuit; and an adder for adding the input signal and the result of the multiplication by the coefficient multiplier. The adder performs add and subtract operations involving the input signal and the output signal supplied via the first unit time delay circuit and via the coefficient multiplier. The cyclic digital filter also comprises a second unit time delay circuit interposingly provided between the coefficient multiplier and the adder. In operation, the coefficient of the coefficient multiplier is adjusted to maintain, in the presence of the second unit time delay circuit, the characteristics of the cyclic digital filter in effect when the second unit time delay circuit is absent.

REFERENCES:
patent: 4751663 (1988-06-01), Yamazaki
patent: 4811263 (1989-03-01), Hedley et al.
patent: 4920507 (1990-04-01), Takeda
patent: 4972356 (1990-11-01), Williams
patent: 5089981 (1992-02-01), Cabot
Signal Processing IV: Theories and Applications vol. 2, 5 Sep. 1988, Grenoble, FR pp. 755-758, XP 124742 KWAN et al. `efficient high speed delayed multipath one-dimensional recursive digital filter architecture`.
Electronics Letters vol. 25, No. 15, 20 Jul. 1989, Enage GB pp. 982-983, XP72014 Kaneko `alternative implementation of systolic recursive digital filters`.

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