Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
1999-11-02
2001-10-16
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S118000
Reexamination Certificate
active
06304207
ABSTRACT:
This Application claims the benefit of Korean Application No. 50978/1998 filed on Nov. 26, 1998, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a cyclic analog/digital converter, and in particular, to an analog/digital converter capable of preventing a digital signal from being mistakenly outputted due to a mis-operation of an internal comparator.
2. Description of the Related Art
In general, a digital signal may be processed by many useful digital processes. This applies equally to audio information, video information or information corresponding to changes in other physical parameters. In order to perform various digital techniques on a digital signal, an analog signal should first be converted to a digital signal with certain bits.
FIG. 1
is a block diagram illustrating a conventional cyclic analog/digital converter including: a first multiplexer
10
; a sample/hold until
12
; a doubling amplifier
14
; a comparator
16
; a second multiplexer
18
; and a voltage subtracter
20
. The first and second multiplexers
10
and
18
each includes three input ports (a-c) and an output port (d), respectively. The input port (b) functions as a control port. The voltage subtracter
20
includes two input ports (a, b) and an output port (c). The doubling amplifier
14
outputs an output signal from the sample/hold unit
12
as it is when the most significant bit (MSB) of the digital signal is determined. The doubling amplifier
14
amplifies the output signal from the sample/hold unit
12
two times when the next-succeeding bit of the digital signal is determined.
The operation of the conventional cyclic analog/digital converter will now be described.
When an analog signal V
IN
is inputted through the input port (a) of the first multiplexer
10
, the first multiplexer
10
selectively outputs to its output port (d) the analog signal V
IN
and an output signal from the subtracter
20
inputted through the input port (c) according to a control signal V
CON
level applied to the input port (b). For example, the first multiplexer
10
outputs the analog signal V
IN
when the control signal V
CON
is at a high level, and outputs the output signal from the subtracter
20
when the control signal V
CON
is at a low level. Here, the control signal V
CON
is at a high level only at the time of sampling the analog signal V
IN
. In all other cases, the control signal V
CON
is always at a low level.
The analog signal V
IN
outputted from the first multiplexer
10
is sampled in the sample/hold unit
12
and inputted to the doubling amplifier
14
. The doubling amplifier
14
outputs the output signal from the sample/hold unit
12
at it is to the comparator
16
in the MSB determination. The comparator
16
compares the sampled analog signal V
IN
inputted through a non-inverting terminal (+) with a reference signal V
REF
inputted through an inverting terminal (−), outputs a high-level output signal V
OUT
when the output signal from the doubling amplifier
14
is greater than the reference signal V
REF
, and outputs a low-level output signal V
OUT
when the output signal from the doubling amplifier
14
is smaller than the reference signal V
REF
. Accordingly, the output signal V
OUT
from the comparator
16
is a most significant bit (MSB) of the digital signal with N bits.
The second multiplexer
18
is similar to the first multiplexer
6
in its structure and operation.
The input port (b) of the second multiplexer
18
is a control port using the output signal V
OUT
from the comparator
16
as a control signal. The input port (a) of the second multiplexer
18
receives the reference signal V
REF
and the input port (c) is grounded. As a result, the second multiplexer
18
outputs the reference signal V
REF
when the output signal V
OUT
from the comparator
16
is at a high level, and outputs a ground voltage V
SS
when the output signal V
OUT
thereof is at a low level.
The voltage subtracter
20
subtracts the output signal from the amplifier
14
inputted through its input port (a) and the output signal from the first multiplexer
18
inputted through its input port (b), and provides a subtraction result to the input terminal (c) of the first multiplexer
10
through its output port (c). However, the control signal V
CON
inputted to the input port (b) of the first multiplexer
10
is maintained at a low level at this time. Thus, the output signal from the subtracter
20
is applied to the sample/hold unit
12
through the output port (d).
The sample/hold unit
12
holds the output signal from the first multiplexer
10
, and provides it to the doubling amplifier
14
. The doubling amplifier
14
amplifies the output signal from the sample/hold unit
12
two times, and outputs it to the comparator
16
. Accordingly, the comparator
16
compares the output signal from the doubling amplifier
14
with the reference signal V
REF
, and outputs the high-level or low-level output signal V
OUT
. As a result, the output signal V
OUT
from the comparator
16
is set to be a next-succeeding bit value of the digital signal.
Accordingly, a desired N bits digital can thus be obtained by repeatedly carrying out the above-described process.
As illustrated in
FIG. 1
, the conventional cyclic analog/digital converter has a structure for consecutively cycling the sampled analog signal V
IN
as many times as the desired number of bits, and is mostly used to obtain the precise digital signal in a low-velocity operation.
Here, the comparator
16
determines the size of the signal to be converted. Therefore, the performance and structure of the comparator
16
is very important.
In general, an operational amplifier is used as the comparator. However, an operational amplifier usually generates an output offset voltage because parameters used for its input terminal are not exactly identical to one another. Therefore, in order to remove the output offset voltage, a circuit for applying an input offset voltage is required. The input offset voltage is strongly influenced by a change of temperature or supply power. Consequently, the comparator may cause a mis-operation of the analog/digital converter, thus outputting a wrong result due to an internally or externally generated offset voltage value or a change thereof.
Accordingly, in the conventional cyclic analog/digital converter, the comparator may operate abnormally due to the offset voltage value or a temporary change thereof, thereby causing a serious problem in an application system where precise operations are important.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a cyclic analog/digital converter that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a cyclic analog/digital converter which can convert an analog signal to a digital signal.
Another object of the present invention is to provide a cyclic analog/digital converter which can provide a precise digital signal, regardless of variations in the input offset of a comparator.
A further object of the present invention is to provide a cyclic analog/digital converter which can provide a precise digital signal regardless of environmental temperature variations and/or related supply power variations.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereon as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described, a cyclic analog/digital converter of the present invention includes a first multiplexer selectively outputting an analog signal and a first input signal purs
Hyundai Electronics Industries Co,. Ltd.
Morgan & Lewis & Bockius, LLP
Wamsley Patrick
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