Cycle time optimization for self-timed read only memory compiler

Details Cycle time optimization for self-timed read only memory compiler Cycle time optimization for self-timed read only memory compiler

1997-09-25

1999-12-14

Teska, Kevin J.

Static information storage and retrieval

Magnetic bubbles

Guide structure

3651852, 365210, G06F 1750, G11C 506

Patent

active

060028580

ABSTRACT:
The present invention, generally speaking, takes into account the programming of a particular ROM in order to calibrate and more nearly optimize the timing of the ROMs timing unit. In one embodiment of the invention, a dummy line is less than fully populated with transistors (loads) in accordance with the greatest degree to which a corresponding actual line is populated with transistors. The dummy line may be a word line or a bit line. Furthermore, both a dummy word line and a dummy bit line may be provided. In accordance with a further embodiment of the invention, if the complement of the number of transistors in the least populated line is less than the number of transistors in the most populated line, then the memory map of the ROM may be uniformly inverted, with the output of the ROM also being inverted. Line loading and cycle time are therefore decreased, allowing for higher speed ROM operation.

REFERENCES:
patent: 4541077 (1985-09-01), Rapp
patent: 5377153 (1994-12-01), Guritz et al.

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