Cycle slip framing system and method for selectively...

Details Cycle slip framing system and method for selectively... Cycle slip framing system and method for selectively...

2005-11-29

2005-11-29

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

C370S506000, C375S371000

Reexamination Certificate

active

06970115

ABSTRACT:
A system and method are provided for synchronizing a frame of related bits output from a deserializer to the related bits serially fed to the deserializer. Synchronization is achieved by overcoming a slip bit problem by selectively increasing the frame clock cycle during times in which the slip bit occurs. The deserializer is controlled by a clock generator that can include a counter which generates the frame clock. The counter can be asynchronously or synchronously reset, without any glitches occurring within the deserializer and, thus, avoiding any invalid bits output from the deserializer. The asynchronous reset forces the counter to a deterministic state, and the synchronous reset sets the counter to a valid state. In each instance, however, resets do not impart glitches to the deserializer and the deserializer output frame is maintained synchronous to related bits serially fed to the deserializer.

REFERENCES:
patent: 4674088 (1987-06-01), Grover
patent: 5128940 (1992-07-01), Wakimoto
patent: 6154509 (2000-11-01), Bishop
patent: 6625240 (2003-09-01), Miyahara
patent: 6696995 (2004-02-01), Foley et al.
patent: 6876630 (2005-04-01), Shim

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