Customizable three metal layer gate array devices

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

257259, H01L 2702

Patent

active

056799675

ABSTRACT:
Three metal layer customizable gate array devices and techniques to customize them are disclosed. Such a device incorporates an integrated circuit blank having a plurality of transistors and at least three metal layers. A plurality of fusible links interconnects said plurality of transistors into an inoperable circuit. A laser ablative etch resistant coating is formed over the device. Later, the coating is ablated by laser at locations overlaying designated fuse locations. The device is then etched for selectably removing some of the fusible links, thereby converting the inoperable integrated circuit blank into an operable gate array device.

REFERENCES:
patent: 3925684 (1975-12-01), Gaskill
patent: 4124899 (1978-11-01), Birkner
patent: 4197555 (1980-04-01), Uehara
patent: 4233671 (1980-11-01), Gerzberg
patent: 4238839 (1980-12-01), Redfern
patent: 4240094 (1980-12-01), Mader
patent: 4295149 (1981-10-01), Balyoz
patent: 4325109 (1982-04-01), Pander
patent: 4356504 (1982-10-01), Tozun
patent: 4412237 (1983-10-01), Matsumura
patent: 4455495 (1984-06-01), Masuhara
patent: 4476478 (1984-10-01), Nozuchi
patent: 4536949 (1985-08-01), Takayama
patent: 4590589 (1986-05-01), Gerzberg
patent: 4651190 (1987-03-01), Suzuki
patent: 4677452 (1987-06-01), Zommer
patent: 4700214 (1987-10-01), Johnson
patent: 4758745 (1988-07-01), Elganal
patent: 4795720 (1989-01-01), Kawanabe
patent: 4924287 (1990-05-01), Orbach
N.H.E. Weste et al. "Principles of CMOS VLSI Design, A System Perspective", Addison-Wesk, (Jun. 1988) pp. 241-244, 370, 374.
North, J. et al. "Laser Coding . . . " IEEE Int'l of Solid State Devices, vol. SC-11, No. 4, Aug. 1976, pp. 500-505.
Schuster, S. "Selective Metallization . . . " IBM Tech Disc. Bull. vol. 15, No. 2, Jul. 1972, pp. 551-552.
Raffel, J.I. et al. "A Wafer Scale . . . " IEEE, Journal of Solid State Circuits, vol. SC-20, No. 1, Feb. 1985.
Disclosed Figures BA-1, BA-2, and BA-3 of U.S. Pat. No. 5,049,969.
C.J. Boisuert, "One Day Prototype Laser . . . ", 8079 Electro/86.alpha.Mini/Micro Northeast, 11 (1986) Conference Record, Los Angeles CA US. pp. 1-4.
R.M. Fisher, "Nonvolatile Memories" IEEE International Solid State Circuits Conference, vol. 25, Feb. 1982, NY USA pp. 114-115.
Ono, K "A Method for Producing a Semiconductor for Integrated Circuit", Kokai JP 53-78789 Japan (English Translation).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Customizable three metal layer gate array devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Customizable three metal layer gate array devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Customizable three metal layer gate array devices will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1008955

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.