Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2005-05-10
2005-05-10
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
Reexamination Certificate
active
06892172
ABSTRACT:
This system represents a customizable simulation model of an ATM/SONET Framer for System Level Verification and Performance-Characterization. An Asynchronous Transfer Mode (ATM) data processing ASIC interfaces with a Media Access Control (MAC) device that presents an electrical data path interface, called Universal Test & Operations PHY Interface for ATM (UTOPIA), using ATM protocol on the ASIC side and simplex optical interfaces using Synchronous Optical Network (SONET) protocol on the network side. Such a MAC device, commonly referred to as ATM/SONET Framer, provides one Receive and one Transmit interface to the network at various SONET line rates such as 155.52 Mbps (OC-3), 622.08 Mbps (OC-12), 2488.32 Mbps (OC-48), etc. The ATM and the SONET interfaces operate on different clock frequencies and thus represent two distinct clocking domains. The data interchange between the two clocking domains is achieved via FIFO buffer elements and associated control and status signals.
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Singh Raj Kumar
Weaver Laura Ann
Cockburn Joscelyn G.
Teska Kevin J.
Thangavelu Kandasamy
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