Customizable logic integrated circuit with multiple-drain transi

Details Customizable logic integrated circuit with multiple-drain transi Customizable logic integrated circuit with multiple-drain transi

1990-09-28

1992-05-26

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 3072991, H03K 19017

Patent

active

051171279

ABSTRACT:
Disclosed is a logic integrated circuit for which the time of switching over between two logic states, 0 and 1, is adjustable. In a logic operator such as an inverter, the switch-over time, at the output, is a function of the current put through by the load transistor or by the signal transistor. This time is adjustable, either as rising time or as fall time, by the replacement of at least one single-drain transistor by a multiple-drain transistor, the throughput rate of which is fixed by the number of connected drains. The disclosed device can be applied to pre-diffused (Si) circuits or pre-implanted (GaAs) circuits.

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Proceedings of the IEEE, vol. 72, No. 6, Jun. 1984, pp. 670-689, IEEE, N.Y., US; E. T. Lewis: "Optimization of device area and overall delay for CMOS VLSI designs" *FIGS. 2, 3, 15-18; p. 671, line 46--p. 675, line 31; p. 676, line 36--p. 688, line 22*.
Patent Abstracts of Japan, vol. 8, No. 8 (E-221), 13 Jan. 1984; JP-A-58 173 868 (Mitsubishi Denki K.K.) Dec. 10, 1983.
Patent Abstracts of Japan, vol. 4, No. 59 (E-009), 2 May 1980; & JP-A-55 030 287 (Nissan Motor Co., Ltd) Apr. 3, 1980.

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