Cursor memory

Details Cursor memory Cursor memory

1997-08-18

1999-11-09

Sax, Steven

Computer graphics processing and selective visual display system

Display driving control circuitry

Controlling the condition of display elements

345145, G06F 1520

Patent

active

059823666

ABSTRACT:
First and second pattern data constituting cursor pattern data are stored separately in banks (101a, 101b). A cursor memory body (101) simultaneously outputs the first and second pattern data from the banks (101a, 101b). Therefore, a read circuit (102) can simultaneously output the first and second pattern data through a port (P2) with a simple control. With this configuration, an easy-controllable cursor memory can be provided.

REFERENCES:
patent: 4868548 (1989-09-01), Gelvin
patent: 4987411 (1991-01-01), Ishigami
patent: 5295254 (1994-03-01), Ogawa
patent: 5313577 (1994-05-01), Meinerth et al.
patent: 5321806 (1994-06-01), Meinerth et al.
patent: 5737502 (1998-04-01), Shimada
1994 IEEE International Solid-State Circuits Conference "A 320 MHz CMOS Triple 8b DAC with On-Chip PLL and Hardware Cursor", David Reynolds, pp. 50-51.
1993 IEEE Custom Integrated Circuits Conference "A 200-MHz 8-kb SRAM Macro For Video Applications", Todd Williams, et al., pp. 25.6.1 to 25.6.3.

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