Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Converting input voltage to output current or vice versa
Reexamination Certificate
2001-10-09
2003-02-18
Nguyen, Minh (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Converting input voltage to output current or vice versa
C327S538000, C341S144000, C323S312000
Reexamination Certificate
active
06522175
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a current/voltage converter which converts a current supplied from a current source into a voltage, a current/voltage converter which converts the total current supplied from the current source supplying the current value corresponding to a digital signal, into a voltage, and relates to a D/A converter using the same.
2. Description of the Related Art
FIG. 3A
is a simplified circuit diagram of an example of a current-cell type D/A converter
30
.
Since an example of two-bit D/A converter will suffice for explaining the principle of current/voltage conversion, a two-bit D/A converter will be described hereinafter for simplification. However, the same goes with a n-bit converter.
The current-cell type D/A converter (hereinafter abbreviated as a “DAC”)
30
shown in
FIG. 3A
comprises three current sources
32
,
34
, and
36
which feed respective currents Is
1
, Is
2
, and Is
3
; three changeover switches
38
,
40
, and
42
provided corresponding to these current sources
32
,
34
, and
36
, respectively; and a resistance element
44
(resistance value: R) for current/voltage (or referred to as I/V, hereinafter) conversion. Herein, Is
1
=Is
2
=Is
3
.
The current source
32
is connected between the power supply and the changeover switch
38
, and likewise, the current source
34
is connected between the power supply and the changeover switch
40
, and the current source
36
is connected between the power supply and the changeover switch
42
. Each of the changeover switches
38
,
40
, and
42
is connected so as to switch between the current source and the ground or an analog signal node Vout. The resistance element
44
is connected between the analog signal node Vout and the ground.
In the illustrated DAC
30
, each of the changeover switches
38
,
40
, and
42
is connected to either the node Vout side or the ground side, in response to a digital signal (not shown) inputted to the DAC
30
.
For example, when the digital signal is “00”, all changeover switches
38
,
40
, and
42
are connected to the ground side, and when the digital signal is “01”, the changeover switch
38
is connected to the node Vout side while the changeover switches
40
and
42
are connected to the ground side. Also, when the digital signal is “10”, the changeover switches
38
and
40
are connected to the node Vout side while the changeover switch
42
is connected to the ground side, and when the digital signal is “11”, all changeover switches
38
,
40
, and
42
are connected to the node Vout side.
Each of the current Is
1
, Is
2
, and Is
3
supplied from the respective current sources
32
,
34
, and
36
flows to either the node Vout side or the ground side in accordance with the setting of the changeover switches, as described above. The total current Isig composed of the currents flowing from the current sources
32
,
34
, and
36
to the node Vout side via the respective changeover switches
38
,
40
, and
42
is I/V converted by the resistance element
44
, and outputted as an analog signal vout=R·Isig, as shown in FIG.
3
A.
As shown in
FIG. 3A
, each of the current sources
32
,
34
, and
36
is constituted of, for example, a P-type MOS transistor (hereinafter abbreviated as PMOS) or the like. As shown in
FIG. 3C
, however, the current Is supplied via a PMOS gradually decreases as the voltage Vds between the source and drain of the PMOS decreases. As a result, in
FIG. 3B
, the voltage of the analog signal Vout increases in a manner such that the voltage b
1
>b
2
>b
3
, although the voltage of the analog signal Vout should essentially increase in a manner such that b
1
=b
2
=b
3
. This raises a problem in that linearity failure of the DAC occurs.
Meanwhile, the minimum value of the analog signal Vout outputted from the DAC
30
shown in
FIG. 3A
is 0 V. However, unless the output of the analog signal Vout is shifted in response to the input-output characteristic of the poststage circuit utilizing this analog signal vout, the analog signal Vout cannot be used for the poststage circuit. It is therefore necessary to level-shift the analog signal Vout of the DAC
30
into the range of the optimum input voltages of the poststage circuit, the range being indicated by an double-headed arrow in FIG.
4
A.
FIGS. 4B
,
4
C and
4
D are each circuit diagrams of examples of conventional level shift circuits.
First, a level shift circuit
50
in
FIG. 4B
is arranged to utilize a source follower configuration, and comprises two PMOSs
52
and
54
. The PMOS
52
is connected between a power supply and an analog signal node Vout, and a bias voltage Vb is inputted to the gate thereof. On the other hand, the PMOS
54
is connected between the analog signal node Vout and the ground, and a signal IN is inputted to the gate thereof. As the signal IN, for example, the analog signal node Vout of the DAC
30
shown in
FIG. 3A
is inputted.
In the illustrated level shift circuit
50
, the PMOS
52
supplies a current in response to the bias voltage Vb to the analog signal node Vout side, while the PMOS
54
feeds the current in response to the voltage of the signal IN to the ground side. Thereby, as the voltage of the signal IN increases, the voltage of the analog signal node Vout rises.
However, the level shift circuit
50
utilizing the source follower configuration involve a problem of inherently having an inferior linearity.
Next, a level shift circuit
56
shown in
FIG. 4C
is arranged to add a bias current Ib to the above-described total current Isig, and to I/V convert this summed current. The level shift circuit
56
comprises a current source
58
which feeds the current corresponding to the total current Isig which flows to the analog output node Vout side of the DAC
30
; a current source
60
for use in the bias current Ib; and a resistance element
62
. Each of the current sources
58
and
60
is connected between the power supply and the analog signal node Vout, and the resistance element
62
is connected between the node Vout and the ground.
In this level shift circuit
56
, the total current Isig and the bias current Ib are summed up, and this summed current (Isig+Ib) is I/V converted by the resistance element
62
, and outputted as an analog signal Vout=(Isig+Ib)·R.
In this level shift circuit
56
utilizing the bias current Ib, however, when the potential of the analog signal Vout is increased by R·Ib, the amplitude of the Vds of the PMOSs of the current sources
32
,
34
, and
36
in
FIG. 3A
is correspondingly reduced. This raises a problem in that the output amplitude decreases.
Then, a level shift circuit
64
shown in
FIG. 4D
is arranged to utilize an operational amplifier, and comprises a current source
66
which feeds the current corresponding to the total current Isig which flows to the analog output node Vout side of the DAC
30
; an operational amplifier
68
; and a resistance element
70
. The current sources
66
is connected between the power supply and the negative input terminal of the operational amplifier
68
. The positive input terminal of the operational amplifier
68
is connected to the ground, and the resistance element
70
is connected between the negative input terminal of the operational amplifier
68
and the output terminal (analog signal Vout).
In this level shift circuit
64
, the analog signal becomes Vout=−R·Isig. That is, the polarity of the analog signal Vout is inverted. This creates a problem in that a wide range of power supply voltage is required in order to secure the amplitude of analog signal Vout.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to solve the problems caused by the above-described conventional arts and to provide a current/voltage converter and a D/A converter using this which are capable of eliminating linearity failure, and which can level-shift the potential of an analog signal in response to the input-output characterist
Serizawa Chie
Takada Masatoshi
Ueno Masayuki
Kawasaki Microelectronics Inc.
Nguyen Minh
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