Current transient reduction for VLSI chips

Details Current transient reduction for VLSI chips Current transient reduction for VLSI chips

1990-04-23

1991-12-17

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307262, 307269, 307475, 328 75, 328155, H03K 520

Patent

active

050737309

ABSTRACT:
Described is a circuit arrangement for controlling peak transient current on data buses of VLSI chips. The circuit arrangement includes a phase lock loop (PLL) with a voltage control oscillator (VCO) made up of high speed inverter circuits that generate very short time interval pulses that are used to control the switching sequence of drivers onto the buses. As a result, the transients are distributed over a relatively short time interval and data throughput on the buses is not adversely affected.

REFERENCES:
patent: 3603810 (1971-09-01), Clayson
patent: 4112380 (1978-09-01), Thatcher
patent: 4484154 (1984-11-01), Pavin
patent: 4574345 (1986-03-01), Konesky
patent: 4626716 (1986-12-01), Miki
patent: 4713621 (1987-12-01), Nakamura et al.
patent: 4754164 (1988-06-01), Flora et al.

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