Current switching circuitry

Details Current switching circuitry Current switching circuitry

2000-08-08

2001-12-11

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

Reexamination Certificate

active

06329940

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to current switching circuitry for use, for example, in digital-to-analog converters (DACs).
2. Description of the Related Art
FIG. 1
of the accompanying drawings shows parts of a conventional digital-to-analog converter (DAC) of the so-called “current-steering” type. The DAC
1
is designed to convert an m-bit digital input word (D
1
-Dm) into a corresponding analog output signal.
The DAC
1
includes a plurality (n) of identical current sources
2
1
to
2
n
, where n=2
m
−1. Each current source
2
passes a substantially constant current I. The DAC
1
further includes a plurality of differential switching circuits
4
1
to
4
n
corresponding respectively to the n current sources
2
1
to
2
n
. Each differential switching circuit
4
is connected to its corresponding current source
2
and switches the current I produced by the current source either to a first terminal, connected to a first connection line A of the converter, or a second terminal connected to a second connection line B of the converter.
Each differential switching circuit
4
receives one of a plurality of control signals T
1
to Tn (called “thermometer-coded signals” for reasons explained hereinafter) and selects either its first terminal or its second terminal in accordance with the value of the signal concerned. A first output current I
A
of the DAC
1
is the sum of the respective currents delivered to the differential-switching-circuit first terminals, and a second output current I
B
of the DAC
1
is the sum of the respective currents delivered to the differential-switching-circuit second terminals.
The analog output signal is the voltage difference V
A
-V
B
between a voltage V
A
produced by sinking the first output current I
A
of the DAC
1
into a resistance R and a voltage V
B
produced by sinking the second output current I
B
of the converter into another resistance R.
In the
FIG. 1
DAC the thermometer-coded signals T
1
to Tn are derived from the binary input word D
1
-Dm by a binary-thermometer decoder
6
. The decoder
6
operates as follows.
When the binary input word D
1
-Dm has the lowest value the thermometer-coded signals T
1
-Tn are such that each of the differential switching circuits
4
1
to
4
n
selects its second terminal so that all of the current sources
2
1
to
2
n
are connected to the second connection is line B. In this state, V
A
=0 and V
B
=nIR. The analog output signal V
A
-V
B
=−nIR.
As the binary input word D
1
-Dm increases progressively in value, the thermometer-coded signals T
1
to Tn produced by the decoder
6
are such that more of the differential switching circuits select their respective first terminals (starting from the differential switching circuit
4
1
) without any differential switching circuit that has already selected its first terminal switching back to its second terminal. When the binary input word D
1
-Dm has the value i, the first i differential switching circuits
4
1
to
4
i
select their respective first terminals, whereas the remaining n-i differential switching circuits
4
i+1
to
4
n
select their respective second terminals. The analog output signal V
A
-V
B
is equal to (
2
i-n)IR.
FIG. 2
shows an example of the thermometer-coded signals generated for a three-bit binary input word D
1
-D
3
(i.e. in this example m=3). In this case, seven thermometer-coded signals T
1
to T
7
are required (n=2
m
−1=7).
As
FIG. 2
shows, the thermometer-coded signals T
1
to Tn generated by the binary-thermometer decoder
6
follow a so-called thermometer code in which it is known that when an rth-order signal Tr is activated (set to “1”), all of the lower-order signals T
1
to Tr-1 will also be activated.
Thermometer coding is popular in DACs of the current-steering type because, as the binary input word increases, more current sources are switched to the first connection line A without any current source that is already switched to that line A being switched to the other line B. Accordingly, the input/output characteristic of the DAC is monotonic and the glitch impulse resulting from a change of 1 in the input word is small.
FIG. 3
shows a previously-considered form of differential switching circuit suitable for use in a digital-to-analog-converter such as the
FIG. 1
converter.
This differential switching circuit
4
comprises first and second PMOS field effect transistors (FETs) S
1
and S
2
. The respective sources of the transistors S
1
and S
2
are connected to a common node CN to which a corresponding current source (
2
1
to
2
n
in
FIG. 1
) is connected. The respective drains of the transistors S
1
and S
2
are connected to respective first and second output nodes OUTA and OUTB of the circuit which correspond respectively to the first and second terminals of each of the
FIG. 1
differential switching circuits.
Each transistor S
1
and S
2
has a corresponding driver circuit
61
or
62
connected to its gate. A corresponding one of the thermometer-coded signals T is applied to the input of the driver circuit
6
1
, whilst a signal {overscore (T)} complementary to the signal T is applied to the input of the driver circuit
6
2
. Each driver circuit buffers and inverts its received input signal T or {overscore (T)} to produce a switching signal SW
1
or SW
2
for its associated transistor S
1
or S
2
such that, in the steady-state condition, one of the transistors S
1
and S
2
is on and the other is off. For example, as indicated in
FIG. 3
itself, when the input signal T has the high level (H) and the input signal {overscore (T)} has the low level (L), the switching signal SW
1
(gate drive voltage) for the transistor S
1
is at the low level L, causing that transistor to be ON, whereas the switching signal SW
2
(gate drive voltage) for the transistor S
2
is at the high level H, causing that transistor to be OFF. Thus, in this condition, all of the input current flowing into the common node CN is passed to the output node OUTA and no current passes to the output node OUTB.
Referring back to
FIG. 1
, in the
FIG. 1
DAC the voltages V
A
and V
B
of the first and second connection lines A and B of the DAC vary in use of the DAC according to the value of the binary input word D
1
-Dm. This means that the potentials of the output nodes OUTA and OUTB of the differential switching circuit
4
also vary in use of the DAC. The transistors S
1
and S
2
have an appreciable parasitic capacitance. These parasitic capacitances must be charged or discharged whenever the differential switching circuit is switched over. The amount of charge that is charged or discharged is then dependent upon the change in the output voltages V
A
and V
B
of the DAC from one code to the next, resulting in a switching delay at the DAC output that is dependent upon the DAC output voltage. If, for example, the DAC is used to synthesise a sinewave at a selected frequency (for example 100 MHz) the output-voltage-dependent delay manifests itself as pulse width modulation at the DAC output. In a high-speed precision DAC this degrades the first-order performance of the DAC significantly. Furthermore, another problem is that the output conductances of the transistors S
1
and S
2
at the instant of switch-over depend weakly on the actual output voltages V
A
and V
B
of the DAC. This also degrades the DAC performance in high-precision applications.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention there is provided current switching circuitry comprising: a plurality of circuitry segments, each having first and second connection nodes through which first and second controllable currents pass respectively when the current switching circuitry is in use, and switch circuitry for changing the respective magnitudes of the first and second controllable currents in dependence upon a switching signal applied to the segment; a first combiner, connected with the respective first connectio

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