Current switching circuit

Details Current switching circuit Current switching circuit

2002-12-05

2004-08-31

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Utilizing three or more electrode solid-state device

C327S108000, C327S404000, C327S322000, C327S328000

Reexamination Certificate

active

06784720

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to current switching circuits employing an inverter constituted by a p-channel MOS transistor and an n-channel MOS transistor in a Si-CMOS integrated circuit (IC) or a pnp bipolar transistor and an npn bipolar transistor in a Si-bipolar junction transistor (BJT IC), for example, a current switching circuit for switching output data, which is used for a current mode logic (CML) mode selector circuit and, more particularly, to a current switching circuit in which even if a supply voltage larger than a breakdown voltage of constituent transistors is used, it is guaranteed that voltages applied to the transistors do not exceed the breakdown voltage.
2. Description of the Prior Art
On account of remarkable progress of miniaturization of Si-CMOS processing and Si-BJT processing in recent years, Si-CMOS and Si-BJT ICs have high-speed response characteristics equivalent to or better than those of GaAs devices. Thus, the Si-CMOS and the Si-BJT ICs have rapidly expanded their fields of application to optical communication ICs and radio communication ICs, operating at frequencies exceeding several GHz and act as key devices for lowering production cost of each system.
High-speed performance obtained by miniaturization of transistors brings about drop of a device breakdown voltage. It has so far been a general practice that in order to secure reliability of a circuit, a regulator or the like reduces a supply voltage of the circuit lower than a device breakdown voltage from a supply voltage specified for each system. However, in case an output amplitude approximate to the breakdown voltage is necessary in a circuit in which a switching transistor and a current source transistor are vertically stacked on each other as in a differential circuit, the supply voltage of the circuit should be set higher than the device breakdown voltage. If the differential circuit and a current switching circuit are used in combination under these circumstances, a problem arises that a voltage not less than the breakdown voltage is surely applied to one of a p-channel MOS transistor or a pnp bipolar transistor and an n-channel MOS transistor or an npn bipolar transistor, thereby resulting in device breakdown.
FIG. 17
shows one example of a configuration of a conventional current switching circuit employing a CMOS IC. The conventional current switching circuit of
FIG. 17
includes a positive power source
1
having a positive voltage Vdd, a negative power source
2
having a negative voltage Vss, a signal input terminal IN, signal output terminals OUT
1
and OUT
2
, n-channel MOS transistors Q
1
, Q
2
and Q
10
for supplying an output current to the signal output terminal OUT
1
and a resistance element
11
having a resistance R
1
. The resistance element
11
determines a drain current flowing through the n-channel MOS transistor Q
2
. The conventional current switching circuit further includes a p-channel MOS transistor Q
3
, an n-channel MOS transistor Q
4
, n-channel MOS transistors Q
5
and Q
13
for supplying an output current to the signal output terminal OUT
2
and a resistance element
12
having a resistance R
2
. A CMOS inverter
20
is constituted by the p-channel MOS transistor Q
3
and the n-channel MOS transistor Q
4
. The resistance element
12
determines a drain current flowing through the n-channel MOS transistor Q
5
.
In the conventional current switching circuit of
FIG. 17
, it is supposed, for example, that the positive power source
1
is grounded and the negative voltage Vss supplied to the negative power source
2
satisfies a relation of (|Vss|>2×Vth) where Vth is, for example, a positive threshold voltage of the transistors Q
1
to Q
5
. Initially, a case is considered in which the signal input terminal IN is at high level upon reception of, for example, the positive voltage Vdd. In this case, since a gate-source voltage Vgs
1
of the transistor Q
1
and a gate-source voltage Vgs
2
of the transistor Q
2
become larger than the threshold voltage Vth, the transistors Q
1
and Q
2
are turned on and thus, a drain current Id
2
flows through both of the transistors Q
1
and Q
2
. The drain current Id
2
is determined by the resistance R
1
of the resistance element
11
and a voltage across opposite ends of the resistance element
11
.
Since a gate voltage Vg
2
(≠Vss) generated in the transistor Q
2
in response to the drain current Id
2
is applied to a gate terminal of the transistor Q
10
, a drain current Id
10
flows through the transistor Q
10
in response to a gate-source voltage of the transistor Q
10
. If a drain voltage of the transistor Q
11
is biased in a saturation area, the drain current Id
10
is substantially determined by a ratio of a gate width Wq
2
of the transistor Q
2
to a gate width Wq
10
of the transistor Q
10
, i.e., (Wq
2
/Wq
10
) and a relation of {Id
10
=Id
2
×(Wq
10
/Wq
2
)} is obtained. The drain current Id
10
flows to the signal output terminal OUT
1
.
The signal input terminal IN is also connected to gate terminals of the p-channel MOS transistor Q
3
and the n-channel MOS transistor Q
4
. Since the signal input terminal IN has the positive voltage Vdd, a gate-source voltage Vgs
3
of the p-channel MOS transistor Q
3
is smaller than the threshold voltage Vth, so that the p-channel MOS transistor Q
3
is turned off. On the other hand, since a gate-source voltage Vgs
4
of the n-channel MOS transistor Q
4
becomes larger than the threshold voltage Vth, the n-channel MOS transistor Q
4
is turned on and a drain voltage of the n-channel MOS transistor Q
4
drops to the negative voltage Vss.
Thus, since an output from the CMOS inverter
20
, namely, a junction of a drain terminal of the p-channel MOS transistor Q
3
and a drain terminal of the n-channel MOS transistor Q
4
has the negative voltage Vss, electric current does not flow through the resistance element
12
and the transistor Q
5
, so that a gate voltage Vg
5
of the transistor Q
5
also has the negative voltage Vss. Since this gate voltage Vg
5
(=Vss) of the transistor Q
5
is applied to a gate terminal of the transistor Q
13
, a gate-source voltage Vgs
13
of the transistor Q
13
becomes smaller than the threshold voltage Vth and thus, a drain current does not flow through the transistor Q
13
. Therefore, there is no electric current flowing to a drain terminal of the transistor Q
13
from the signal output terminal OUT
2
.
Then, a case is considered in which the signal input terminal IN is at law level upon reception of, for example, the negative voltage Vss. In this case, since electric current does not flow through the transistors Q
1
and Q
2
and the resistance element
11
, there is no electric current flowing from the signal output terminal OUT
1
. Since the signal input terminal IN has the negative voltage Vss, the gate-source voltage Vgs
3
of the p-channel MOS transistor Q
3
becomes larger than the threshold voltage Vth and thus, the channel MOS transistor Q
3
is turned on. On the other hand, since the gate-source voltage Vgs
4
of the n-channel MOS transistor Q
4
becomes smaller than the threshold voltage Vth, the n-channel MOS transistor Q
4
is turned off and the drain voltage of the n-channel MOS transistor Q
4
rises to the positive voltage Vdd. Therefore, an output from the CMOS inverter
20
has the positive voltage Vdd.
Hence, a voltage is applied across opposite ends of the resistance element
12
and thus, a drain current Id
5
flows through the transistor Q
5
. The drain current Id
5
is determined by the resistance R
2
of the resistance element
12
and a voltage across opposite ends of the resistance element
12
. Since the gate voltage Vg
5
generated in the transistor Q
5
in response to the drain current Id
5
is applied to the gate terminal of the transistor Q
13
, a drain current Id
13
generated in response to the gate-source voltage Vgs
13
(=Vg
5
−Vss) of the transistor Q
13
flows from the si

Affiliated with

Also associated with

Rating

Current switching circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Current switching circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Current switching circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3321456