Coded data generation or conversion – Analog to or from digital conversion – With particular solid state devices
Patent
1994-02-16
1995-08-29
Hoff, Marc S.
Coded data generation or conversion
Analog to or from digital conversion
With particular solid state devices
341153, H03M 178
Patent
active
054464579
ABSTRACT:
A digital-to-analog converter has a bias block that provides first and second voltage outputs, and a bit cell having a switch for selectively connecting either a first or a second summing node to a current flow path depending upon the state of a binary input signal. An output bipolar transistor and a current source are connected in series between a supply voltage and a reference potential. A first MOS transistor is connected in the current flow path with its gate connected to the bipolar transistor. A base current compensating second MOS transistor is connected between the supply voltage and a base of the output bipolar transistor with its gate connected to the first voltage output of the amplifier. A resistor is connected between the base of the output bipolar transistor and the second voltage output of the amplifier. When a plurality of bit stages are provided, the resistor of each of the plurality of bit cells is sized according to a position of its associated cell in the bit order. The resistors may be sized as a power of 2 according to a position of its associated cell in the bit order, or, except for a most significant bit cell may be sized 2 times larger than the resistor of the most significant bit cell, with a plurality of equally sized resistors connecting adjacent bit cells in an R-2R network.
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Arrambide Joseph
Bachand Richard A.
Hoff Marc S.
Jorgenson Lisa K.
SGS-Thomson Microelectronics Inc.
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