Current starved DAC-controlled delay locked loop

Details Current starved DAC-controlled delay locked loop Current starved DAC-controlled delay locked loop

2005-08-09

2005-08-09

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S147000

Reexamination Certificate

active

06927612

ABSTRACT:
A delay locked loop circuit with improved restart features. The circuit includes a clock input, a clock output, a divider circuit, phase detector and control logic. The circuit includes a means for implementing a binary search of outputs from the control logic for generating a calibration bit, which is applied to the transmission on an output line.

REFERENCES:
patent: 5334952 (1994-08-01), Maddy et al.
patent: 6204705 (2001-03-01), Lin
patent: 6239633 (2001-05-01), Miyano
patent: 6269051 (2001-07-01), Funaba et al.
patent: 6323705 (2001-11-01), Shieh et al.
patent: 6492852 (2002-12-01), Fiscus
patent: 6570420 (2003-05-01), Trivedi et al.
patent: 6691214 (2004-02-01), Li et al.

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