Current stacked bandgap reference voltage source

Details Current stacked bandgap reference voltage source Current stacked bandgap reference voltage source

2000-02-03

2001-06-05

Tso, Edward H. (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C323S316000

Reexamination Certificate

active

06242897

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to reference voltage sources and particularly to on-chip current stacked band gap reference voltage sources.
On-chip voltage reference sources employ voltage stacked bipolar transistor array bandgap structures to derive reference voltages for use on the chip. Stacked bipolar arrays reduce sensitivity to operational amplifier offsets, resistor mismatches, and current mirror mismatches, without employing laser trimming or autozeroing clocks. One advantage of a stacked array is that a large &Dgr;Vbe voltage can be derived to enhance the tolerance of the circuit by minimizing errors due to offsets and mismatches due to reduced gain to the output.
Stacked reference voltage sources reduce the effect of error voltages, such as offset due to amplifier, resistor and current mirror mismatches, by increasing the contribution of the &Dgr;Vbe voltage. By employing an area-ratioed stack of matched bipolar transistors, a +TC reference voltage is produced which is N times the &Dgr;Vbe voltage, where N is the number of stacks in the array. The +TC voltage is proportional to K (N&Dgr;Vbe+Vos) where Vos is the error voltage due to offset. Thus, the offset is effectively reduced by a factor of N. It will be appreciated that the error voltage is multiplied by the constant K, but the constant K may be reduced by increasing the number of levels in the stack of the array. See Ahuja et al., “A Programmable CMOS Dual Channel Interface Processor for Telecommunications Applications”,
IEEE Journal on Solid
-
State Circuits
, Vol. SC-19, No. 6, pp. 892-899 (December 1984).
However, voltage stacked bipolar transistor arrays require significant supply headroom for operation. For example, three stacked Vbe diode drops of an array of three bipolar transistors requires approximately a headroom of 2.1 volts (assuming 0.7 volt diode drops). Moreover, the transistors exhibit a temperature coefficient of about −2 mV/° C., so when operating at extreme temperature conditions (such as −50° C.), the required supply headroom increases to approximately 2.55 volts for three diode drops. While reducing the stack size to two transistors reduces the required supply headroom to about 1.4 volts (1.7 volts at −50° C.), the reduction of the array size requires increasing constant K to achieve the desired reference voltage, and is not as effective in reducing sensitivity to offsets and mismatches. Further, in modern IC processes, where power supplies may he of the order of 1.8 volts ±10%, voltage stacked arrays are not realizable.
SUMMARY OF THE INVENTION
The present invention is directed to an on-chip voltage reference source operating in the current domain instead of voltage domain, thereby allowing implementation employing a single diode drop, thereby reducing required supply headroom.
In a preferred form of the invention a current stacked reference voltage source is provided to generate a predetermined reference voltage. The reference voltage source includes a plurality of current generators each generating a current representing a first design voltage; each current generator has no more than a single diode drop to generate the current. A gain circuit is responsive to the currents generated by the current generators to supply a gain voltage representing the sum of the first design voltages. A summing circuit sums the gain voltage and a second design voltage to derive the predetermined reference voltage.
Another form of the invention provides an integrated circuit chip current having a stacked reference voltage circuit. The reference voltage circuit includes a plurality of current generators, a summing node and an output circuit. Each current generator has first, second and third current sources having control nodes coupled together. A differential amplifier has a first input coupled to the first current source, a second input coupled to the third current source and an output coupled to the control nodes of the current sources. A first semiconductor device has a control node coupled to the second current source. A first impedance is coupled to the control node of the first semiconductor device in series with the third current source. A fourth current source supplies current to the summing node representative of current supplied by the third current source. The summing node sums current supplied by each of the fourth current sources of the current generators. The output circuit includes a fifth current source, and a second semiconductor device. A control node of the second semiconductor device is coupled to the summing node. A second impedance circuit is coupled to the control node of the semiconductor device in series with the fifth current source. An output is coupled to the controlled node of the second semiconductor device to provide the reference voltage.
In a preferred form of the invention, each current generator further includes a third semiconductor device coupled between a supply node and the first current source. The first and third current sources supply different current values and the first and third semiconductor devices have different active areas. The first impedance provides a voltage (&Dgr;Vbe) to the control node of the first semiconductor device based on a difference between the current values supplied by the first and third current sources and the active areas of the first and third semiconductor devices.
In another preferred form of the invention, each of the first impedances provides a first impedance value (R1) and the second impedance provides a second impedance value (R1+R2) greater than the first impedance value. The second semiconductor device operates with the second impedance to provide a gain constant to a voltage at the control node of the second semiconductor device of (1+R2/R1).
In another preferred form of the invention, the second impedance provides a voltage to the control node of the second semiconductor device having a value of N(1+R2/R1)&Dgr;Vbe, where N is the number of current generators.
In another preferred form of the invention, the second semiconductor device has a diode drop voltage (Vbe) between its control node and controlled node. Thus, the output supplies the reference voltage having a value of N(1+R2/R1)&Dgr;Vbe+Vbe.
In another form of the invention, a method of generating a reference voltage is provided by which a plurality of currents are generated, each representing a first design voltage. The currents are summed, and the reference voltage is derived based on the sum of the plurality of currents. In one form of the invention, the derivation of the reference voltage is performed by deriving a gain voltage based on the sum of the plurality of currents, and summing the gain voltage with a second design voltage.


REFERENCES:
patent: 4636710 (1987-01-01), Stanojevic
patent: 4896094 (1990-01-01), Greaves et al.
patent: 5307007 (1994-04-01), Wu et al.
patent: 5325045 (1994-06-01), Sundby
patent: 6016051 (2000-01-01), Can
“A Programmable CMOS Dual Channel Interface Processor for Telecommunications Applications” by Bhupendra K. Ahuja et al.,IEEE Solid-State Circuits, vol. SC-19, No. 6, pp. 892-899, Dec. 1984.

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