Current source using merged vertical bipolar transistor...

Details Current source using merged vertical bipolar transistor... Current source using merged vertical bipolar transistor...

1999-07-27

2001-07-03

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S548000, C257S549000, C257S552000

Reexamination Certificate

active

06255713

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to an integrated circuit current source, and more particularly, to a current source using a merged vertical bipolar transistor that is based on gate induced drain leakage (GIDL) current.
BACKGROUND OF THE INVENTION
Conventional CMOS semiconductor devices, such as the n-channel ETOX cell, are often fabricated by a twin-well process or a triple-well process. As seen in
FIG. 1
, the triple-well process can provide a parasitic vertical pnp
101
bipolar transistor as well as a parasitic vertical npn
103
bipolar transistor. These transistors are typically used for crucial circuit applications (e.g. voltage reference) in CMOS VLSI. The n+ and p+ source and drain structures can serve as the n+ and p+ emitters. The p-well and n-well can act as the bases and the deep n-well and p+ substrate as collectors. These bipolar transistors are in “common collector” or “emitter-up” configuration.
These vertical bipolar transistors of the prior art have several limitations.
First, they share the same p-substrate or deep n-well as their collectors and therefore can only be configured in “common collector” mode. Second, the bipolar amplification of the pnp
101
and npn
103
are typically less than three in modern CMOS technology (i.e. 0.35 &mgr;m and below) due to the limitation of the well depth (as base width) and a retrograded well doping profile (desirable in advanced CMOS process for suppressing latch-up).
The vertical bipolar transistors
101
and
103
are often used to form current sources.
FIGS. 3A and 3B
show prior art current sources, with
FIG. 2A
showing a current source
301
using two npn transistors
303
a
and
303
b
and
FIG. 3B
showing a current source
351
using two pnp transistors
353
a
and
353
b
. The output current I
o
can be designed to be proportional to the reference current I
ref
by adjusting the ratio of the emitter areas of the transistors. For example, in
FIG. 3A
, the following relationship can be stated:
 I
o
≈I
ref
[A
e2
/A
e1
]
where A
e2
is the area of the emitter of transistor
303
b
and A
e1
is the area of the emitter of transistor
303
a.
Similarly, in
FIG. 3B
, the following relationship can be stated:
I
o
≈I
ref
[A
e2
/A
e1
]
where A
e2
is the area of the emitter of transistor
353
b
and A
e1
is the area of the emitter of transistor
353
a.
The conventional designs of
FIG. 3A and 3B
are relatively large because of the interconnections required. Thus, what is needed is a new design for a current source that overcomes the disadvantages of the prior art and provides other advantages.
SUMMARY OF THE INVENTION
A current source formed in a p-type substrate is disclosed. The current source comprises: a deep n-well formed within said p-type substrate; a buried n+ layer formed within said deep n-well; a p-well formed within said deep n-well and atop said buried n+ layer; an isolation structure surrounding said p-well and extending from the surface of said substrate to below the level of said p-well; a n+ reference structure formed within said p-well; a gate formed above said p-well, said gate separated from said substrate by a thin oxide layer, said gate extending over at least a portion of said n+ reference structure; and a n+ output structure formed within said p-well; wherein an input reference current is provided to said n+ reference structure and an output current is provided by said n+ output structure.


REFERENCES:
patent: 5495124 (1996-02-01), Terashima
patent: 4-222117 (1992-08-01), None

Affiliated with

Also associated with

Rating

Current source using merged vertical bipolar transistor... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Current source using merged vertical bipolar transistor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Current source using merged vertical bipolar transistor... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2556711