Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-05-03
2003-09-02
Tran, M. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185260
Reexamination Certificate
active
06614687
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a non-volatile, integrated circuit memory array such as an electrically erasable, electrically programmable read-only memory (EEPROM) array. In particular, the invention relates to an improved method and apparatus for programming floating gate memory cells.
2. Description of the Related Art
For flash memory devices, a memory array consists of a row and column arrangement of memory cells where each memory cell includes a floating gate transistor. Programming of a cell may be accomplished by applying drain and gate bias on a cell with the source grounded or with a small source bias to inject electrons to the floating gate. Erasure may be accomplished by applying a negative voltage on the gate and positive bias on the source (or drain) with drain (or source) floating. Process dependent characteristics of EEPROM transistors, including channel width/length and oxide thickness, affect operating characteristics of the device during the programming cycle. These process dependent characteristics may exhibit themselves as variations in the electrical characteristics of memory cells fabricated from different wafers, on different dies within a wafer or between memory cells on a single die. Cells with short/wide channels, a.k.a. fast bit cells, usually program faster than cells with long
arrow channels, a.k.a. slow bit cells.
A number of problems with prior art EEPROM/EPROM devices may be traced to process dependent variations in the electrical characteristics of memory cells. These include a wide range of threshold voltage distributions within an array as well as increase in power consumption. Process dependent variations result in program and erasure speed which differs from cell to cell. This results in wide bandwidth &Dgr;Vt of program voltages for fast and slow bit cells about a desired program voltage. This distribution is particularly undesirable when the cell being programmed is a multilevel cell (MLC). Unlike an ordinary memory cell in which one bit of information is stored, an MLC stores more than one bit of information. This capability requires a compact Vt distribution which is difficult to achieve using current programming techniques. To achieve such compact Vt distribution, bit-by-bit program verification is required for memory arrays which implement multilevel cells. The drawback of this method is that much longer programming time is consumed as compared to the single level cell system. Power consumption is also effected by process dependent variations of memory cells. Programming of memory cells may be accomplished by applying fixed drain/source bias and stepped/ramped gate bias to program cells. Variations in the electrical characteristics of memory cells result in programming current per cell, which may vary from 200uA-400uA, so that the power consumption cannot be well controlled.
Several methods have been proposed to reduce the threshold voltage distribution of programmed cells within a memory array. One prior method is to intentionally increase the passive resistance of the EEPROM cells source node. The drawback to this approach is that a passive resistance does not track process variations that effect EEPROM programming efficiency. Another prior art technique to narrow threshold voltage distribution after programming is to alternately program and erase cells in successively smaller steps. Each cell is then checked after each program step to see whether it is properly programmed. This technique requires additional time and circuitry.
Another prior art technique is disclosed in U.S. Pat. No. 5,218,571 entitled “EPROM Source Bias Circuit With Compensation For Processing Characteristics”, issued June 1993. That patent discloses a process tracking circuit used to control the source bias of cells being programmed, so as to remove process dependent program voltage variations between memory arrays.
FIG. 1
is a hardware block diagram of the '571 device. A representative EPROM transistor
104
of a memory array is shown. That cell is coupled to the current source component
102
. There may be multiple current source components
102
within a memory array, all coupled to a common source bias control
100
. The current source component includes one of the following devices: the parallel combination of an N-channel transistor and resistor, a voltage source or current source. Those devices are coupled in series between the floating gate
104
and a ground. The control gate of the device is coupled via signal line
110
to the source bias control which generates a process dependent voltage to drive the device. The process dependent voltage generated by the source bias control depends on the process variability of a single mirror cell within a mirror memory array contained within the source bias control
100
. As the conductivity of the single mirror cell increases, the voltage on signal line
110
decreases. A decrease in the voltage on signal line
110
results in a reduction in the conductivity of the devices within the current source component. Therefore, the conductivity of the current source component(s) rises as the conductivity of the mirror memory cell decreases, and vice-versa. In chips/die with a high conductivity single mirror cell, the current source components coupled to the control will have lower conductivity and vice-versa. Thus, the voltage applied at the source of memory array is inversely related to the reference flash cell's resistance as expressed by the following equation 1:
Vs
(memory array)∝1
/R
cell, where
R
cell is the channel resistance of reference flash cell. Equation 1:
There are several disadvantages to the prior art in approach. First, the circuitry disclosed in the '571 patent effects only inter-wafer/die process variations and not process variations between memory cells on a single chip/die. This results from the fact that there is only one process dependent element, i.e., the source bias control
100
, per memory array. Second, process variability appears to require the mirroring of a significant portion of the memory array within the source bias control. Third, by increasing the source bias to memory array with primarily fast program bit cells, i.e., reducing Vds, the program current may be reduced and the time required to program these memory cells is increased.
What is needed is a programming technique which reduces the effect of process variations between wafers, between dies, and between memory cells on a chip without requiring an increase in programming time.
SUMMARY OF THE INVENTION
A new structure and method with a process tracking current source component to program a flash EPROM memory is proposed. By applying a process dependent current source component which exhibits process variations substantially matching those of the cell being programmed, a self-convergent and high efficiency programming can be achieved. This process tracking current source component provides less current for cells with higher erased Vt and larger current for cell with lower erased Vt.
In an embodiment of the invention, a circuit for programming a floating gate transistor is disclosed. The floating gate transistor includes: gate, drain and source nodes. The circuitry for programming includes a current source component. The current source component couples in series between the floating gate transistor and an electrical sink during a programming interval. The current source component includes an electrical characteristic substantially matching the electrical characteristic of the floating gate transistor.
In an embodiment of the invention an integrated circuit memory module on a semiconductor substrate is disclosed. The integrated circuit memory module includes: an array of floating gate memory cells, decoders, and a plurality of current source components. The array of floating gate memory cells is arranged in M rows and N columns. Each cell includes a floating gate transistor. The floating gate transistor includes: gate, drain and source nodes. The
Chen Ming-Shang
Lin Baw-Chyuan
Lu Wenpin
Wang Mam-Tsung
Beyer Weaver & Thomas LLP
Macronix International Co. Ltd.
Tran M.
LandOfFree
Current source component with process tracking... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Current source component with process tracking..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Current source component with process tracking... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3052391