Current source circuit

Details Current source circuit Current source circuit

2000-09-27

2001-11-20

Berhane, Adolf Deneke (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C323S316000

Reexamination Certificate

active

06320364

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a current source circuit using current mirror circuits.
2. Description of the Prior Art
Today a current source circuit using current mirror circuits is proposed.
FIG. 1
is the circuit diagram of a current source circuit using current mirror circuits. In
FIG. 1
, a current source circuit
1
is comprised of an operational amplifier
2
, an N-channel MOSFET (hereinafter simply called a “MOS transistor”) Q
1
, P-channel MOSFETs (hereinafter simply called a “MOS transistor”) Q
2
and Q
3
that compose a current mirror circuit and a resistor R
1
.
A reference signal (Vref), which is described later, is supplied to the non-inversion input (positive input) of the operational amplifier
2
, and a feedback signal is applied to the inversion input (negative input). The feedback signal applied to the inversion input (negative input) is a voltage value at point A shown in
FIG. 1
, and which is a potential of the connection point between the MOS transistor Q
1
and the resistor R
1
. The output of the operational amplifier
2
is supplied to the gate of the MOS transistor Q
1
and the output turns the MOS transistor Q
1
on/off.
The MOS transistors Q
2
and Q
3
, which compose the current mirror circuit, have the same characteristics and the same mirror current flows in the MOS transistors Q
2
and Q
3
. For example, when a gate voltage is applied to the gate of the MOS transistor Q
1
from the operational amplifier
2
, the MOS transistor Q
1
is turned on, a current flows in the MOS transistor Q
2
. Simultaneously, an output current (mirror current) Iout with the same current value flows in the MOS transistor Q
3
.
The potential at point A is the potential of the reference signal (Vref) of the operational amplifier
2
. Therefore, while the MOS transistor Q
1
is turned on, the voltage applied to the resistor R
1
is Vref and the current (Iref) that flows in the resistor R
1
is the voltage of the reference signal (Vref) divided by the resistance value of the resistor R
1
. This current Iref flows in one direction in the current mirror circuit, and the output current (mirror current) (Iout) shown in
FIG. 1
is the same as the current (Iref).
Therefore, when in the configuration it is assumed that the reference signal varies, the output current (mirror current) also varies in the same way. For example, when a triangular wave is used for the reference signal (Vref), the output current (mirror current) Iout becomes a triangular wave.
In this way, according to the current source circuit shown in
FIG. 1
, the output current varies as the reference signal (Vref) varies and the desired output current can be obtained. However, in the current source circuit, the response speed is slow, which is a problem. This is because the operational amplifier
2
is used and the feedback circuit is used at the same time. Specifically, many transistor circuits are used in the operational amplifiers and it takes much time to drive the circuit. The use of the feedback circuit requires a period of time to return the signal.
FIG. 2
shows that the output current (mirror current) Iout delays from the reference signal (Vref) In
FIG. 2
, a waveform represented by Vref is the reference signal inputted to the operational amplifier
2
, and a dotted waveform represented by Iout indicates the output timing of the output current (mirror current) The output current (mirror current) Iout delays from the reference signal (Vref), and a time lag of time T is generated between the reference signal (Vref) and the output current (mirror circuit) Iout.
This time lag is a problem when the output current (mirror current) Iout is actually used. For example, when the output current (mirror current) Iout is used as an oscillator modulation, the modulation timing is delayed. When a pulse signal is generated using the output current (mirror current) Iout, the pulse signal with a targeted timing cannot be generated due to the delay of the output current (mirror current).
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a current source circuit using current mirror circuits in which the delay of an output current (mirror current) Iout against a reference signal (Vref) is eliminated.
Specifically, it is an object of the present invention to provide a current source circuit that comprises a first current mirror circuit for supplying an output current outside, a second current mirror circuits for driving the first current mirror circuit to which a resistor for generating a reference current corresponding to the output current is connected, a reference voltage supply circuit for setting the reference current that flows in the resistor and a third current mirror circuit for avoiding the influence of the mirror current that flows in the first and second current mirror circuits. The current source circuit needs a start signal which drives the first or second current mirror circuit. When the start signal is applied to the first or second current mirror circuit, a mirror current is generated. After that, the mirror current drives another current mirror circuit. Then, the mirror current corresponding to the reference voltage is also generated in the resistor by connecting the current outputting MOS transistor to the resistor and supplying the reference voltage to the diode connected MOS transistor. Furthermore, the output current (Iout), which is mirror current corresponding to the reference current, is outputted by the first current mirror circuit. Furthermore, current is prevented from flowing in the reference voltage supply circuit by driving the third current mirror circuit.


REFERENCES:
patent: 4004247 (1977-01-01), Van de Plassche
patent: 4897596 (1990-01-01), Hughes et al.
patent: 5021730 (1991-06-01), Smith
patent: 5045773 (1991-09-01), Westwick et al.
patent: 5173656 (1992-12-01), Seevinck et al.
patent: 5446397 (1995-08-01), Yotsuyanagi
patent: 5446409 (1995-08-01), Katakura
patent: 5539302 (1996-07-01), Takimoto et al.
patent: 5774021 (1998-06-01), Szepesi et al.

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