Current source circuit

Details Current source circuit Current source circuit

2001-09-27

2003-07-29

Berhane, Adolf Deneke (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C323S312000

Reexamination Certificate

active

06600303

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims benefit of priority under 35USC §119 to Japanese Patent Application No. 2000-296411 filed on Sep. 28, 2000 in Japan, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
The present invention relates to a current source circuit installed in a semiconductor device.
A current source circuit such as the one shown in
FIG. 1
used as a current source for an operational amplifier has been known. The circuit shown in
FIG. 1
is disclosed in “Analog Integrated Circuit Design for VLSI Designers” by P. R. Gray and R. G. Mayer, 1999, pp307 and pp308.
The current source circuit shown in
FIG. 1
is set in a stable operation mode by turning on a start-up transistor QN
15
to cause decrease in gate potential for PMOS transistors QP
11
, QP
12
and QP
13
that constitute a current mirror circuit.
The PMOS transistors QP
11
and QP
12
of the current mirror circuit, when their sizes are equal, provide the same amount of current to a current path from the PMOS transistor QP
12
to an NMOS transistor QN
12
and a resistor R
11
and to another current path from the PMOS transistor QP
11
to an NMOS transistor QN
11
and a diode D
11
. That same amount of current is also flown to an NMOS transistor QN
13
from the PMOS transistor QP
13
when the transistors QP
12
and QP
13
have the same size.
The NMOS transistor QN
13
and an NMOS transistor QN
14
as a current source for an operational amplifier OP also constitute a current mirror circuit, thus providing a stable current source circuit for the operational amplifier OP.
In this known current source circuit, the minimum voltage VCCmin of a power supply voltage VCC for a stable operation is roughly expressed as below when looking at the current path from the PMOS transistor QP
11
to the NMOS transistor QN
11
and the diode D
11
.
VCCmin=|Vtp|+Vf+
0.3  (1)
In this expression, Vtp is a threshold voltage of the PMOS transistor QP
11
, Vf is a voltage (about 0.6 V) between the anode and cathode of the diode D
11
in forward bias and 0.3 V is a voltage between the drain and source of the NMOS transistor QN
11
.
The expression (1) teaches that the larger the absolute value of a threshold voltage of the PMOS transistor, the higher the minimum power supply voltage VCCmin for a stable operation of a current source circuit.
Power supply voltages have been lowered in accordance with advancement of transistor micro-fabrication for semiconductor memories, etc. In this tendency, however, the minimum voltage VCCmin for a stable operation of a current source circuit will not vary if a threshold voltage of a PMOS transistor is not varied as discussed above, thus obstructing further lowering of power supply voltage.
For example, Vtp=−1 V for a threshold voltage of a PMOS transistor gives about 1.9 V for the minimum voltage VCCmin for a stable operation of a current source circuit according to the expression (1). This means that a power supply voltage for a semiconductor memory cannot be lowered to 1.8 V or less. The minimum voltage VCCmin for a current source circuit can be lowered as an absolute value of a threshold voltage is lowered for each PMOS transistor to be installed in a semiconductor memory.
Decrease in threshold voltage for all PMOS transistors to be installed in a semiconductor memory, however, results in worse cut-off characteristics which will cause a large leak current for a semiconductor memory, thus being difficult for meeting requirements of current to be consumed.
Decrease in threshold voltage for PMOS transistors only for a current source circuit of a semiconductor memory can prevent a leak current from increase. Fabrication of PMOS transistors with different threshold voltages in a semiconductor memory will, however, increase the number of production processes, thus raising production cost.
Therefore, what is required here is a current source circuit that operates by a lower power supply voltage with no change in threshold voltage for PMOS transistors.
SUMMARY OF THE INVENTION
A purpose of the present invention is to provide a current source circuit that operates by a power supply voltage lower than that for known current source circuit.
The present invention provides a current source circuit comprising: a first current path through which a first current is supplied to a first circuit from a first current source via a first terminal, the first circuit having a first device with a specific voltage-current characteristics; a second current path through which a second current is supplied to a second circuit from a second current source having the same current-drive capability as the first current source via a second terminal, the second circuit having a second device with voltage-current characteristics different from that for the first device of the first circuit, characteristic curves in the both voltage-current characteristics being crossing each other at certain voltage and current values; a third circuit connected to the first terminal, that pulls out a current from the first terminal; and a fourth circuit connected to the second terminal, that pulls out a current of the same amount as the current pulled out from the first terminal, from the second terminal, the third and the fourth circuits pulling out excess current components from the first and the second terminals, respectively, so that the first and the second currents become equal to each other.
Moreover, the present invention provides a differential amplifier circuit comprising: a first current path through which a first current is supplied to a first circuit from a first current source via a first terminal; a second current path through which a second current is supplied to a second circuit from a second current source having current-drive capability the same as the first current source via a second terminal, the first and the second circuit being a pair of differential transistors, differential signals being supplied to the gates of the differential transistors; a third circuit connected to the first terminal, that pulls out a current from the first terminal; and a fourth circuit connected to the second terminal, that pulls out a current of the same amount as the current pulled out from the first terminal, from the second terminal, the third and the fourth circuits pulling out excess current currents from the first and the second terminals, respectively, so that the first and the second current become equal to each other.


REFERENCES:
patent: 5825168 (1998-10-01), Kimber
patent: 5920185 (1999-07-01), Ozoe
patent: 6031414 (2000-02-01), Kitamura
patent: 0936627 (1999-08-01), None
M. Gaibotti et al., “A Fast 1Mb EEPROM with 1.8V to 3.6V Operating Voltage”, SGS Thomson R&D, Apr. 1998, pp. 2-8.

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