Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2001-08-14
2003-01-14
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S144000
Reexamination Certificate
active
06507296
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to calibration of current sources and in particular the present invention relates to a clocking scheme for calibration of current sources.
BACKGROUND OF THE INVENTION
Digital-to-analog (D/A) conversion is the process of converting digital codes into a continuous range of analog signal levels. Major factors that determine the quality of performance of DACs are resolution, sampling rate, speed, and linearity. Generally, the accuracy of the DAC's measurement and conversion is specified by the converter's linearity. “Integral linearity” is a measure of linearity over the entire conversion range. It is defined as the deviation from a straight line drawn between the maximum point and through zero (or the offset value) of the conversion range. “Differential linearity” is the linearity between adjacent steps of the analog output. Differential linearity is a measure of the monotonicity of the converter. The converter is said to be monotonic if increasing input values result in increasing output values.
Digital codes are typically converted to analog voltages by assigning a voltage weight, or current weight, to each bit in the digital code and summing the voltage or current weights of the entire code. This type of DAC is called a binary weighted DAC. DACs that produce analog current outputs usually have a faster settling time and better linearity than those that produce a voltage output.
As is well known in the art, a “segmented” DAC design converts digital codes to analog signals by activating a number of weighted segments proportional to the input digital code and summing the activated segments to form the analog output signal. In segmented DACs, two or more reference currents of appropriate ratio dictated by the percentage of segmentation are required to calibrate the current sources in each segment. In non-segmented DACs, reference current sources can be calibrated using a “golden” current source to improve accuracy. Sequentially calibrating numerous current sources, however, can create problems during operation.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a calibration circuit and methodology that can calibrate numerous current sources without adversely affecting operation characteristics.
SUMMARY OF THE INVENTION
The above-mentioned problems with current source calibration and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a current source calibration circuit comprises first and second current sources, a calibration circuit, a switching circuit to selectively couple the first and second current sources to the calibration circuit in response to a pseudo-random clock signal, and a clock generator to provide the pseudo-random clock signal.
In another embodiment, a digital-to-analog (DAC) circuit comprises a plurality of sub-DACs each comprising at least one current source, a calibration circuit coupleable to calibrate the current sources, and a clock generator circuit coupled to the calibration circuit to provide a clock signal having a random frequency.
A digital-to-analog (DAC) circuit, of an embodiment, comprises a plurality of sub-DACs each comprising, a primary current source, a backup current source, and switching circuitry to couple the primary and backup current sources to calibration circuitry. The DAC includes a clock generator circuit coupled to the switching circuitry to provide a plurality of clock signals each having a random frequency.
A method of calibrating a plurality of current sources comprises generating a clock signal having a random frequency, and coupling the plurality of current sources to a calibration circuit in response to the clock signal.
REFERENCES:
patent: 5666118 (1997-09-01), Gersbach
patent: 5955980 (1999-09-01), Hanna
patent: 6329941 (2001-12-01), Farooqi
patent: 6331830 (2001-12-01), Song et al.
Hassoun Marwan N.
Lee Yvette P.
Chan H. C.
Fogg Slifer & Polglaze
Jean-Pierre Peguy
Xilinx , Inc.
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