Current signatures for IDDQ testing

Details Current signatures for IDDQ testing Current signatures for IDDQ testing

1997-04-25

2001-01-16

Nguyen, Vinh P. (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

06175244

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates generally to the testing of CMOS integrated circuits, and more particularly the invention relates to the use of power supply current (I
DDq
) measurements for the testing of the integrated circuits.
I
DDq
testing is a method for testing VLSI circuits by detecting elevated levels of quiescent current caused by defects in the circuit. As applied today, I
DDq
is measured on a set of test vectors and each measurement from the set is compared to a threshold value. If a measurement is higher than the threshold, the test fails; if all measurements are below the threshold, the test passes.
Despite increasing popularity and ever more widespread use of I
DDq
testing in recent years, an open question still exists as to what level of current to use as the I
DDq
pass/fail threshold. Setting the limit incorrectly carries a heavy penalty. If the limit is too high, bad dies may escape testing, which defeats the purpose of I
DDq
testing aimed at detecting defects that are unlikely to be detected by voltage testing. If the limit is too low, good dies may be rejected, which leads to unnecessary yield loss and, hence revenue loss.
The present invention introduces the notion of a current signature as a means for addressing this problem. The potential of current signatures for allowing dies with harmful defects to be identified—even if they have only a low level of defect current—without imposing a restrictively low pass/fail threshold has been demonstrated via several examples taken from a large CMOS circuit design.
SUMMARY OF THE INVENTION
In accordance with the invention power supply current (I
DDq
) is measured for an integrated circuit undergoing test in response to a plurality of input vectors. The magnitudes of the currents produced by the circuit are compared. A difference between currents is identified as evidence of the presence of an active fault. The active fault current causes steps in the current signature of the device undergoing test. A circuit with an active fault may be less tolerable in the acceptance/rejection criteria than a circuit with no active fault, even if the circuit with no active fault produces a higher level of maximum current, because an active fault results from defects affecting the signal path in the device, which is a high risk and can represent a reliability problem. The location of defects as well as the nature of defects can be determined by comparing a current signature for a device under test with current signatures of circuits having known defects, either by circuit simulation or by previously tested devices with defects.
The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawings.


REFERENCES:
patent: 4710704 (1987-12-01), Ando
patent: 4727318 (1988-02-01), Sakai et al.
patent: 4808915 (1989-02-01), Russell
patent: 4820974 (1989-04-01), Katsura et al.
patent: 4835458 (1989-05-01), Kim
patent: 5025344 (1991-06-01), Maly et al.
patent: 5057774 (1991-10-01), Verhelst et al.
patent: 5059889 (1991-10-01), Heaton
patent: 5321354 (1994-06-01), Ooshima et al.
patent: 5332973 (1994-07-01), Brown et al.
patent: 5371457 (1994-12-01), Lipp
patent: 5392293 (1995-02-01), Hsue
patent: 5410547 (1995-04-01), Drain
patent: 5459737 (1995-10-01), Andrews
patent: 5467026 (1995-11-01), Arnold
patent: 5481551 (1996-01-01), Nakano et al.
patent: 5483170 (1996-01-01), Beasley et al.
patent: 5552744 (1996-09-01), Burlison et al.
patent: 5670892 (1997-09-01), Sporck
patent: 5731700 (1998-03-01), McDonald
patent: 5889408 (1999-03-01), Miller
patent: 5914615 (1999-06-01), Chess
Sreejit Chakravarty, Minsheng Liu, “Algorithms for Current Monitor Based Diagnosis of Bridging and Leakage Faults,” 29thACM/IEEE Design Automation Conference, Paper No. 22.6, pp. 353-356, © 1992 IEEE (Month Unavailable).
R. Rodr{acute over (i)}guez-Monta{tilde over (n)}{acute over (e)}s, J.A. Segura, V.H. Champac, J. Figueras, J.A.Rubio, “Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS,” Univ. Polit{grave over (e)}cnica de Catulunya, Eng. Electr{grave over (o)}nica, Diagonal 649, p9, 08028 Barcelona, Univ. de les Illes Balears, Dept. de F{acute over (i)}scica, Crta. de Valldemossa, 07071 Palma, Spain, International Test Conference 1991, Paper No. 19.3, pp. 510-519, © 1991 IEEE (Month Unavailable).
Samir Naik (Carnegie Mellon University), Frank Agricola (Philips Semiconductors), Wojciech Maly (Carnegie Mellon University), “Failure Analysis of High Density CMOS SRAMs Using Realistic Defect Modeling and IDDQTesting,”IEEE Design&Test of Computers, pp. 13-23, ©Jun. 1993 IEEE.
1H. Balachandran and2D.M.H. Walker,1Department of Electrical Eng., Texas A&M University, College Station, TX 77843,2Department of Computer Science, Texas A&M University, College Station, TX 77843, “Improvement of SRAM-Based Failure Analysis Using Calibrated Iddq Test,” 14thVLSI Test Symposium—1996, pp. 130-136 (Month Unavailable).
Jitendra B. Khare, Student Member, IEEE, Wojciech Maly, Fellow, IEEE, Susanne Griep, and Doris Schmitt-Landsiedel, “Yield-Oriented Computer-Aided Defect Diagnosis,”IEEE Transactions on Semiconductor Manufacturing, vol. 8, No. 2, May 1995, pp. 195-206.
Young-Jun Kwon and D. M. H. Walker, “Yield Learning via Functional Test Data,”Department of Computer Science, Texas A&M University, College Station, TX 77843, International Test Conference, Paper No. 27.2, pp. 626-635, © 1995 IEEE (Month Unavailable).
Robert C. Aitken, “A Comparison of Defect Models for Fault Location with Iddq Measurements,” Design Technology Center—Hewlett-Packard Co., International Test Conference 1992, Paper No. 36.3, pp. 778-787, © 1992 IEEE (Month Unavailable).
Steven D. Millman (Motorola Inc.) and John M. Acken (Intel Corporation), “Diagnosing CMOS Bridging Faults With Stuck-AT, IDDQ, and Voting Model Fault Dictionaries,”IEEE 1994 Custom Integrated Circuits Conference, Paper No. 17.2.1, 17.2.2, 17.2.3, 17.2.4, pp. 409412, © 1994 IEEE (Month Unavailable).
Daniel J. Burns, “Locating High Resistance Shorts in CMOS Circuits by Analyzing Supply Current Measurement Vectors,” International Symposium for Testing and Failure Analysis '89, (ISTFA 89), pp. 231-237 (Month Unavailable).
Luther K. Horning, Jerry M. Soden, Ron R. Fritzmeier, and Charles F. Hawkins, “Measurements of Quiescent Power Supply Current for CMOS ICs in Production Testing,” Reprinted from Proceedings International Test Conference, 1987, pp. 118-127, ©IEEE 1987 (Month Unavailable).
Charles F. Hawkins, Jerry M.Soden, Ronald R. Fritzemeier, and Luther K. Horning, “Quiescent Power Supply Current Measurement for CMOS IC Defect Detection,”IEEE Transactions on Industrial Electronics, vol. 36, No. 2, May 1989, pp. 211-218.
Wojciech Maly and Phil Nigh, “Built-In Current Testing—Feasibility Study,” Department of Electrical and Computer Engineering, pp. 340-343, ©1988 IEEE (Month Unavailable).
Thomas M. Storey and Wojciech Maly, “CMOS Bridging Fault Detection,” International Test Conference 1991, Paper BP1, pp. 1123-1132 (Month Unavailable).
Streejit Chakravarty and Sivaprakasam Suresh (Dept. of Computer Science-State University of New York, Buffalo, NY), “IDDQMeasurement Based Diagnosis of Bridging Faults in Full Scan Circuits,” 7thInternational Conference on VLSI Design, pp. 179-182, Jan. 1994, ©1994 IEEE.
Gattiker, Anne et al., “Current Signatures for Production Testing,” 1996 IEEE International Workshop on IDDQ Testing, Oct. 24-25, 1996, pp. 25-28.
Gattiker, Anne E. et al., “Current Signatures,” Proceedings 14th IEEE VLSI Test Symposium, Apr. 28-May 1, 1996, pp. 112-117.

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