Current sensing and current sharing

Details Current sensing and current sharing Current sensing and current sharing

2000-12-13

2002-07-02

Patel, Rajnikant B. (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S282000

Reexamination Certificate

active

06414469

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to voltage regulator modules (VRMs) and, more particularly, to quasi-square-wave (QSW) interleaved buck converters with current sensing and sharing.
2. Decription of the Prior Art
An evolution in microprocessor technology poses new challenges for supplying power to these devices. The evolution began when the high-performance PENTIUM processor was driven by a non-standard, less-than 5V power supply, instead of drawing its power from the 5V plane on the system board. In order to meet faster and more efficient data processing demands, modem microprocessors are being designed with lower voltage requirements. The processor supply voltage in future generation processors will decrease from 3.3V to 1.1V~1.8V. Meanwhile, since more devices are being packed on a single processor chip and the processors are operating at higher operating frequencies, microprocessors require more aggressive power management. Future generation processor current draw is predicted to increase from 13 A to between 30 A-50 A. These higher currents in turn require special power supplies, known as voltage regulator modules (VRMs), to provide lower voltages with higher current capability for the microprocessors.
TABLE 1
Specifications for current and future VRM
Current
Future
Output Voltage:
2.1
~
3.5 V
1
~
3 V
Load Current:
0.3
~
13 A
1
~
50 A
Output Voltage Tolerance:
±5%
±2%
Current Slew at decoupling Capacitors
1 A
S*
5 A
s
*Current slew rate at today's VRM output is 30 A/uS
Table 1 shows the specifications for current and future VRMs. As the speed of the processor grows, the dynamic loading, and hence the slew rate, of the VRM increases. The current slew rate measures the maximum rate of change current draw based on dynamic loading and voltage across the output terminals of the power supply. These slew rates represent a severe problem for large load changes that are usually encountered in power management systems when the systems shift from sleep mode to active mode and vice versa. In this case, the parasitic impedance of the power supply connection to the load and the parasitic elements of capacitors have a dramatic effect on VRM voltage. Future microprocessors are expected to exhibit higher current slew (from 1 A
S to 8 A
s) and larger current draw. Moreover, the total voltage tolerance will become much tighter. Presently, the voltage tolerance is 5% (for 3.3V VRM output, the voltage deviation can be ±165 mV). In the future, the total voltage tolerance will be 2% (for 1.1V VRM output, the voltage deviation can only be ±33 mV). All these requirements pose serious design challenges.
Most of today's VRMs use conventional buck or synchronous rectifier buck topology. In the future for low-voltage and high dynamic loading applications, the limitations of these topologies become very clear. In order to maintain the voltage regulation of future requirements during the transient, more output filter capacitors and decoupling capacitors will be needed. However, the space of the VRM and motherboard are very limited, increasing capacitors is an impractical approach. To meet future specifications, novel VRM topologies are required.
FIG. 1
shows the conventional buck circuit, which is the most cost-effective approach. Usually, Schottky diodes are used as the rectifier. The upper MOSFET transfers energy from the input and the lower rectifier conducts the inductor current. The control regulates the output voltage by modulating the conduction interval of the upper MOSFET.
FIG. 2
shows a conventional synchronous rectifier buck circuit. This topology increases the efficiency of low output voltage DC-to-DC converters by replacing the rectifier with a MOSFET. Its control and transient response are similar to those of a conventional buck converter.
During the transient, the buck and the synchronous buck exhibit three spikes in the voltage drop.
FIG. 3
shows the transient response of these topologies illustrating the first, second, and third spikes.
FIG. 4
shows the practical VRM load model (processor model) which illustrates the parasitic loops that cause these spikes. The first spike is dominated by loop F
2
, the second spike is dominated by loop F
3
, and the third spike is dominated by loop F
4
. The limitation of these two topologies comes from their large output filter inductance. During the transient, this large inductor limits the energy transfer speed, therefore almost all the energy is provided by capacitors. For future microprocessor applications (Table 1), with its higher load current and tighter voltage tolerance requirements, more decoupling capacitors will be needed to reduce the second spike, and more output bulk capacitors will be needed to reduce the third spike (capacitors are used to reduce equivalent series resistance (ESR) and equivalent series inductance (ESL) and to provide energy.). As a result,
FIG. 5
shows that in order to meet future specifications, about twenty-three (23) times the decoupling capacitors are needed and three (3) times the bulk capacitors are needed when compared with the capacitors used for today's requirement. However, in the future, limited space will be important to power devices that need to be used in parallel to reduce the conduction loss in low-voltage high-current converters to satisfy the efficiency requirements of the VRM. The need for a large quantity of capacitors makes the conventional VRMs impractical and expensive for future microprocessors.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a dc-dc converter for a power supply which is capable of a high current slew.
It is yet another object of the present invention to provide a dc-dc converter which supplies with a fast transient response required when, for example, a load processor changes from sleep mode to active mode.
According to the invention, an interleaved small-inductance buck VRM converter with the novel current sensing and sharing technology to significantly improve the transient response with size minimization. Specifically, two or more buck VRM modules are interleaved or connected in parallel. The resultant current waveform has a fast transient response but with reduced ripples since the ripples in the individual modules mathematically cancel one another. The result is a smooth output current waveform having spikes within an acceptable tolerance limits when for example the load increases due to a connected processor changing from “sleep” to “active” mode. A novel current sensing and sharing scheme between the individual VRMs is implemented using an RC network in each module to detect inductor current for that module. Good current sharing result can be easily achieved. Unlike peak current mode control and average current mode control, with this technology, the converter still has low output impedance and fast transient response. As a result, the VRM can be very cost-effective, high power density, high efficiency and have good transient performance.


REFERENCES:
patent: 4628433 (1986-12-01), Notohamiprodjo
patent: 5477132 (1995-12-01), Canter et al.
patent: 5808453 (1998-09-01), Lee et al.
patent: 6023154 (2000-02-01), Martinez
F. Lee et al., “Power Management for Future Generation of Processors”, Intel Research Council, Thursday, Sep. 11, 1997.

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