Current sense amplifier circuit

Details Current sense amplifier circuit Current sense amplifier circuit

2002-01-09

2002-10-22

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185200, C365S207000

Reexamination Certificate

active

06469937

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a current sense amplifier circuit for detecting a current passing through a memory cell of a nonvolatile semiconductor memory device.
BACKGROUND OF THE INVENTION
FIG. 7
is a diagram illustrating an example of a conventional current sense amplifier circuit.
In
FIG. 7
, M
1
denotes an N type MOS transistor, having a source connected to a ground voltage and a gate connected to an input terminal N
1
of the circuit. M
2
denotes a P type MOS transistor, having a source connected to a power supply voltage, a gate connected to the ground voltage, and a drain connected to a drain of the N type MOS transistor M
1
. M
3
denotes an N type MOS transistor, having a source connected to the input terminal N
1
of the circuit and a gate connected to a drain of the P type MOS transistor M
2
. M
4
denotes a P type MOS transistor, having a source connected to the power supply voltage, a gate connected to the ground voltage, and a drain connected to a drain of the N type MOS transistor M
3
. X
1
denotes a first inverter, having an input terminal connected to the drain of the P type MOS transistor M
4
and an output terminal connected to an output terminal N
2
of the circuit. M
5
denotes a memory cell of a floating gate type MOS transistor, and storage is realized using two states, i.e., a state where a current flows and a state where no current flows, by controlling the threshold voltage of the memory cell. M
6
denotes a bit line selection gate transistor.
The N type MOS transistor M
1
and the P type MOS transistor M
2
constitute a second inverter X
2
having an input terminal connected to the input terminal N
1
of the circuit and an output terminal connected to the gate of the N type MOS transistor M
3
.
In the conventional current sense amplifier circuit so constructed, the output from the inverter X
2
controls the N type MOS transistor M
3
according to the voltage at the input terminal N
1
, whereby the voltage at the input terminal N
1
is controlled. That is, when the voltage at the input terminal N
1
is lower than the threshold voltage of the inverter X
2
, the inverter X
2
outputs a “H” level voltage, whereby the N type MOS transistor M
3
is turned on, and the input terminal N
1
is charged. On the other hand, when the voltage at the input terminal N
1
is higher than the threshold voltage of the inverter X
2
, the inverter X
2
outputs a “L” level voltage, whereby the N type MOS transistor M
3
is turned off, and charging is stopped. Accordingly, the inverter X
2
serves as a clamper to limit the voltage at the input terminal N
1
to the threshold voltage of the inverter X
2
.
With the voltage at the input terminal N
1
being held as described above, when the memory cell is in the state where a current flows, the memory cell current flows from the P type MOS transistor M
4
through the N type transistor M
3
and, at this time, the voltage at the drain of the P type MOS transistor M
4
becomes lower than the power supply voltage according to the drain current vs. source-to-drain voltage characteristics of the P type MOS transistor M
4
, and a “H” level voltage is output to the output terminal N
2
of the circuit by the inverter X
1
. On the other hand, when the memory cell is in the state where no current flows, the voltage at the drain of the P type MOS transistor is equal to the power supply voltage, and a “L” level voltage is output to the Qutput terminal of the circuit by the inverter X
1
.
In the conventional current sense amplifier circuit, the detected amount of current depends on the characteristics of the P type MOS transistor M
4
, and the characteristics of the P type MOS transistor M
4
intersect the characteristics of the memory cell in the erase state and the write state, whereby the operating power supply voltage is restricted.
Further, in the conventional current sense amplifier circuit, two states, i.e., whether the memory cell current exceeds a predetermined amount of current or not, are detected. So, when data is read from a memory cell, which is set in multiple states, by changing the load on the P type MOS transistor M
4
, it is difficult to secure a wide range of operating power supply voltage. Therefore, the conventional circuit is not adapted to readout of data from a memory cell which is set in multiple states (three or more states).
SUMMARY OF THE INVENTION
The present invention is made to solve the above-described problems and has for its object to provide a current sense amplifier circuit that secures a wide range of operating power supply voltage, and that is adaptable to readout of data from a memory cell which is set in multiple states (three or more states).
Other objects and advantages of the invention will become apparent from the detailed description that follows. The detailed description and specific embodiments described are provided only for illustration since various additions and modifications within the scope of the invention will be apparent to those of skill in the art from the detailed description.
In order to solve the problem about the restriction of the operation range with respect to the power supply voltage, a current sense amplifier circuit of the present invention is provided with a reference current generator and a current comparator, and the current comparator compares a reference current according to the characteristics of a memory cell with a memory cell current. Thereby, a broad operation range is obtained with respect to the power supply voltage or the like.
Further, in order to realize detection of current in the memory cell which is set in multiple states, a current sense amplifier circuit of the present invention is provided with plural sets of reference current generators and current comparators, and the reference current generators generate reference currents of different amounts corresponding to plural states the memory cell can take, and the current comparators compare the respective reference currents with the memory cell current. Therefore, it is possible to detect the current in the memory cell which is set in multiple states, thereby increasing the recording density of the memory cell.


REFERENCES:
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patent: 5805500 (1998-09-01), Campardo et al.
patent: 5838612 (1998-11-01), Calligaro et al.
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patent: 5973959 (1999-10-01), Gerna et al.
patent: 6181602 (2001-01-01), Campardo et al.
patent: 6324098 (2001-11-01), Condemi et al.
patent: 6333885 (2001-12-01), Bedarida et al.
patent: 6351416 (2002-02-01), Fuchigami et al.

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