Current reference circuit

Details Current reference circuit Current reference circuit

2000-08-21

2002-03-05

Pascal, Robert (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including current mirror amplifier

C330S277000, C323S315000

Reexamination Certificate

active

06353365

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an integrated current reference circuit.
BACKGROUND OF THE INVENTION
It is known to provide a constant current generating circuit using two interconnected current mirrors, of which one current mirror is of p FETs and the other is of n FETs. Such circuits have traditionally required one of the branches of the current generator to contain a resistor.
Use of resistors in integrated circuits is not desirable for a number of reasons, for instance because of the temperature dependence thereof, because of the area occupied by a resistor and the difficulty of manufacture.
The present invention therefore aims to at least partly mitigate the difficulties of the prior art.
SUMMARY OF THE INVENTION
According to the present invention there is provided an integrated current reference circuit comprising a first current mirror and a second current mirror, each current mirror having a respective controlling node and a respective controlled node, the controlling node of the first current mirror being connected to the controlled node of the second current mirror and vice-versa, wherein the first current mirror comprises a first FET and a second FET, said first and second FETs each having a respective source, gate and drain terminal, said second FET further having a substrate terminal, the first FET having its gate and drain electrode connected together in common and forming the controlling node of the first current mirror and the second FET having its gate connected in common with the commoned gate and drain of the first FET, and further comprising voltage offset circuitry connecting the source electrodes of the first and second FETs to a supply terminal, the substrate of the first FET being connected to its source and the substrate terminal of the second FET being connected to the supply terminal.
Preferably the second current mirror comprises a first FET and a second FET, the first FET of the second current mirror having a gate and a drain electrode connected together in common and the second FET of the second current mirror having a gate connected to the commoned gate and drain of the first FET of the second current mirror and further comprising an output FET having a gate connected in common to the gate of the second FET of the second current mirror.
Advantageously the first FET of the second current mirror has a smaller current carrying capacity than the second FET of the second current mirror.
Advantageously said first and second FETs of the first current mirror are p FETs and said first and second FETs of the second current mirror are n FETs.
Conveniently said voltage offset circuitry comprises a first offset element connected between the source electrode of the first FET of the first current mirror and said supply terminal and a second offset element connected between the source electrode of the second FET of the first current mirror and said supply terminal.
Preferably said first and second offset elements comprise diode-connected p FETs.


REFERENCES:
patent: 4994688 (1991-02-01), Horiguchi et al.
patent: 5949278 (1999-07-01), Oguey
patent: 6084391 (2000-07-01), Onodera
patent: 6160393 (2000-12-01), Ahn et al.
patent: 0 733 961 (1996-09-01), None
patent: 2 071 953 (1981-09-01), None
Standard Search Report performed in the corresponding United Kingdom application.
Zhenhua Wang, Two CMOS Large Current-Gain Cells With Linearly Variable Gain and Constant Bandwidth, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, US, IEEE Inc. New York, vol. 39, No. 12 pp. 1021-1024, XP000362832.

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