Static information storage and retrieval – Powering – Conservation of power
Reexamination Certificate
2002-09-04
2004-04-06
Auduong, Gene (Department: 2818)
Static information storage and retrieval
Powering
Conservation of power
C365S210130, C365S226000, C365S189090, C327S541000
Reexamination Certificate
active
06717880
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to a sense amplifier of a semiconductor memory chip and, more particularly, to reducing the consumption of an electric current caused by a simultaneous driving of two circuits by differing the reference voltages of a discharge voltage and a power generation circuit in a part of a discharging period, when reducing the power voltage that has been raised after over-driving a sense amplifier.
2. Description of Related Art
As semiconductors become more integrated and low powered, achievement of simultaneous low driving voltages and high speed becomes desirable. Accordingly, as a driving voltage is lowered, methods have been attempted to drive a sense amplifier smoothly in a dynamic RAM (DRAM), such as through a sense amplifier over driving method.
If the data stored in a cell are selected according to the operation of a bit line sense amplifier (to be referred to as a ‘sense amplifier’ hereinafter), they are charge-shared and come in as bit lines having the potential of the voltage for bit line precharge (VBLP). Here, in the pull-up operation from a bit line precharge voltage VBLP to a cell power voltage DVDD, since the cell power voltage CVDD is low and, thus, the difference between the cell power voltage CVDD and the voltage for bit line precharge (VBLP) is not large, it takes a long time to raise the VBLP to the desired level of the cell power voltage CVDD. To solve this problem, the size of a transistor for pull-up in the sense amplifier may be made larger, but this approach increases the size of a semiconductor memory chip, and often there are limitations imposed on the size of a particular memory chip. Therefore, an alternative solution has been to utilize an over driving method.
Referring to
FIGS. 1 and 2
, the operation of a conventional over-driving method will be described hereinafter.
The cell data selected by a word line are transferred to a bit line and the bit line pair is diverged. Here, the bit lines are diverged by the width of &Dgr;V, and the width is determined by the ratio of the cell capacitance and the bit line capacitance. The width may range from tens of millivolts to hundreds of millivolts. The sense amplifier is driven by the diverged width and creates a value sufficient to read/write data. The next operation begins during this operation of sense amplifier.
In a first over-driving period of the sense amplifier operation, a first sense amplifier enable signal SA_EN_
1
is supplied to a MOS transistor MOS
1
of an external power voltage unit
110
(in case of an NMOS transistor, an “H” or HIGH signal; and in the case of a PMOS transistor, an “L” or low signal) thereby enabling the MOS transistor MOS
1
. In the initial period, an external power voltage VEXT, which is higher than a cell power voltage CVDD, is supplied to the sense amplifier
130
through the path A along the MOS
1
and the restore line RTO and thus the potential of the restore line RTO rises sharply.
When the potential of the restore line RTO rises to a predetermined level and the over-driving period has been finished, in a second driving period, a second sense amplifier enable signal SA_EN_
2
is supplied to a MOS transistor MOS
2
of the cell power voltage unit
120
thereby enabling the MOS transistor MOS
2
. At that moment, the cell power voltage CVDD is applied to the sense amplifier
130
through the MOS transistor MOS
2
and the restore line RTO and place the sense amplifier
130
into a pull-up state and maintains that state.
During the operation, a current may flow from the external power voltage unit
110
, which supplies relatively high voltage to the cell power voltage unit
120
which provides a relatively low voltage, thus raising the cell power voltage CVDD. In particular, when the sense amplifier
130
is operated continuously, the influx into the cell power voltage unit
120
appears large. In the part A of
FIG. 2
, the restore line RTO ascends excessively, and the cell power voltage CVDD is raised as well by the effect therefrom. The use of an over-driving circuit, which operates the driving of the sense amplifier
130
, which reads/writes data for high speed processes of a semiconductor memory chip, improves the performance of the memory core. However, there is a problem that the electric current consumed is excessive due to the potential gap between the two powers.
To solve this problem, a method is utilized that compares the actual cell power voltage CVDD and the reference cell power voltage VREF in the middle of or after the sense amplifier operates and conducts over-driving. If the actual cell power voltage CVDD is higher than the reference power voltage VREF, the actual cell power voltage CVDD is lowered to a desired level. However, due to the delay time in sensing between the circuit (i.e., a discharge circuit) which lowers the actual cell power voltage CVDD that has been raised and the CVDD power generation circuit that raises the reference cell power voltage VREF when the actual cell power voltage CVDD falls below the reference cell power voltage VREF, the level of the actual cell power voltage CVDD fluctuates during this operation and much electric current is consumed unnecessarily. This operation will be described more in detail, hereinafter.
FIG. 3
is a block diagram describing the structure of a semiconductor memory device in accordance with another conventional over-driving method.
As shown in
FIG. 3
, a semiconductor memory device of the conventional over-driving scheme includes a core unit
310
of a semiconductor memory chip using an external power voltage VEXT and the cell power voltage CVDD. A cell power voltage generation unit
320
is included for generating a cell power voltage CVDD used in the core unit
310
and a cell power voltage discharge unit
330
is included for lowering the potential of the cell power voltage CVDD that has been raised by the operation of the core unit
310
.
First, in the over-driving period, the cell power voltage CVDD is raised according to over driving by the external power voltage VEXT, and in the first discharging period, a cell power voltage discharge unit
330
operates and compares the actual cell power voltage CVDD with the reference voltage VREF. As the actual cell power voltage CVDD is raised, the cell power voltage discharge unit
330
operates and pulls down the actual cell power voltage CVDD to the level of the reference voltage VREF. When the actual cell power voltage CVDD falls below the reference voltage VREF by discharging during the discharge period, the discharging operation is not immediately halted. This is due to a delay in the sensing caused by operation time of transistors within the cell power voltage discharge unit
330
. Thus, the actual cell power voltage CVDD falls below the reference voltage. The actual cell power voltage CVDD is then raised due to the operation of the cell power voltage generation unit
320
via charging, but does not terminate when the actual cell power voltage CVDD reaches the reference voltage through charging due to sensing delay time caused by operation time of the transistors in the voltage generation unit
320
, thereby overshooting the reference voltage. Hence, a current flows from the external power voltage VEXT to the cell power voltage CVDD, and from the cell power voltage CVDD to the source voltage VSS, respectively, owing to the repeated operations of the cell power voltage generation unit
320
and the cell power voltage discharge unit
330
, causing a dampened oscillation as shown in FIG.
4
. This current is consumed unnecessarily, and as the operation of a semiconductor memory chip gets faster, the amount of the current consumption increases drastically.
SUMMARY OF THE INVENTION
The present disclosure provides a current reducing device in a sense amplifier over driver scheme of a semiconductor memory chip that can reduce the amount of electric current consumed unnecessarily during the discharging operation by differing the reference voltages of a cell power voltage discharge unit and a cell p
Auduong Gene
Hynix Semiconductor Inc
Marshall & Gerstein & Borun LLP
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