Current output circuit with controlled holdover capacitors

Details Current output circuit with controlled holdover capacitors Current output circuit with controlled holdover capacitors

1999-09-03

2001-04-24

Wong, Peter S. (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C323S316000

Reexamination Certificate

active

06222357

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a current output circuit for sampling predetermined reference current and outputting current corresponding to sampled current, and more particularly to a current output circuit suitable for use as a drive circuit for a plurality of light emitting elements of a display or the like.
2. Related Background Art
In a conventional display for displaying characters and images which display has a number of light emitting elements such as light emitting diodes (hereinafter called an LED), for example, as shown in
FIG. 3
, a constant current circuit is constituted of D/A converters B
1
, B
2
, . . . corresponding to LED elements D
1
, D
2
, . . . Each LED element is supplied with a predetermined drive current via a corresponding one of current output terminals T
1
, T
2
, . . . of the D/A converters to drive the LED element. The light emission amount of the LED element changes with the drive current of the D/A converter. Each D/A converter is of a current output type. The output current of each D/A converter is determined by digital data set to the D/A converter and input reference voltages at terminals Vref(+) and Vref(−), where Vref(+) is a high reference voltage input terminal and Vref(−) is a low reference voltage input terminal.
FIG. 4
is a circuit diagram of a usual D/A converter B of a current output type. In
FIG. 4
, A
1
represents an operational amplifier, Rf represents a feedback resistor used for converting input reference voltages Vref(+) and Vref(−) into current, Q
1
, Q
2
, . . . represent NPN transistors constituting a constant current circuit with binary weight, R
1
, R
2
, . . . represent resistors, S
1
, S
2
, . . . represent switching devices, and T represents and output terminal.
A problem associated with the driver circuit for multi-channel LED elements shown in FIG.
3
and using current output type D/A converters shown in
FIG. 4
, is a variation in output current values at respective channels. A variation in output current values is greatly influenced by a variation in resistance values of the feedback resistors Rf. As the number of output channels of an multi-channel LED element driver circuit made of a semiconductor integrated circuit increases, the variation in output current values increases. In order to reduce the variation, it is necessary to adjust the resistance value of each feedback resistor Rf through laser trimming or the like, so that the manufacture cost rises. Since it is necessary to provide D/A converters as many as the number of channels, the area of a wafer or chip occupied by the integrated circuit increases necessarily.
As an alternative multi-channel LED element driver circuit, a circuit such as shown in
FIG. 5
may be used in which one current source (DAC) is used and switching devices and sampling circuits with capacitors are incorporated. In
FIG. 5
, DAC represents a current output type D/A converter, M
1
, M
2
, M
3
, . . . represent PMOS transistors constituting constant current circuits, S
1
, S
2
, S
3
, . . . and C
1
, C
2
, C
3
, . . . represent switching devices and capacitors constituting sample-hold circuits, D
1
, D
2
, D
3
, . . . represent light emitting elements such as LED, and reference numeral
1
represents a power source terminal.
In operation of this circuit, first the switching devices S
1
and S
4
are turned on and the other switching devices are tuned off to charge the hold capacitor C
1
with an output current of DAC. The charge voltage of the capacitor C
1
is determined by the output current of DAC and the characteristics of a gate source voltage V
GS
versus a drain current I
D
of the PMOS transistor M
1
. In accordance with this voltage, the other transistor M
2
constituting a current mirror circuit together with the transistor M
1
drives the light emitting element with constant current. Similarly, when the switching devices S
1
and S
4
are turned off and the switching devices S
2
and S
5
are turned on, the hold capacitor C
2
is charged and, in accordance with this charge voltage, the transistor M
4
drives the light emitting element D
2
with constant current.
Since only one DAC of the circuit shown in
FIG. 5
determines the output current of each channel, a variation in output currents as in the drive circuit using a number of DAC's shown in
FIG. 3
does not exist. However, relative precisions of the transistors M
1
and M
2
and resistors R
1
, R
2
, the transistors M
3
and M
4
and resistors R
3
and R
4
, and the like respectively constituting the current mirror circuit may cause the output current variation. However, since elements of this circuit can be disposed near each other, a current variation can be reduced more than the circuit shown in FIG.
3
.
With the circuit shown in
FIG. 5
, however, as a high speed sample/hold operation is performed, a variation in output currents becomes large. The reason for this is as follows. The charge speed of the hold capacitor is determined by the capacitance of the capacitor and the output current of DAC. The charge speed is further dependent upon the output current of DAC. As the capacitance of the capacitor is made smaller, a hold voltage called a hold step generated when the switching devices S
4
to S
6
are turned off becomes larger. Therefore, a variation in output currents of the transistors M
2
, M
4
, M
6
, . . . constituting the constant current circuits becomes large relative to the output current set to DAC.
The discharge speed of the hold capacitor is determined by the mutual conductance g
m
of the PMOS transistor M
1
, M
3
, M
5
, . . . whose gate and drain are short-circuited. The mutual conductance g
m
is dependent upon a ratio (W/L) of the gate width W to the gate length L of each transistor. It is necessary to increase the mutual conductance and hence the gate width W in order to speed up the discharge speed of the hold capacitor.
However, if the gate width of the PMOS transistor M
1
, M
2
, M
3
, . . . is increased, the area occupied in an integrated circuit necessarily increases and at the same time a parasitic capacitor of the drain formed between the drain and semiconductor substrate or the like becomes large. This parasitic capacitance is multiplied by the number of output channels. Therefore, the parasitic capacitance hinders the high speed sample/hold operation. The precision of the current mirror circuit shown in
FIG. 5
is also degraded by an unbalance of the drain-source voltages V
DS
of a pair of transistors constituting the current mirror circuit. This also causes a variation in output currents.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a current output circuit capable of setting an output current at high speed and with high precision, reducing a variation in output currents of respective channels, and reducing an area of the circuit occupied in a semiconductor integrated chip.
According to one aspect of the present invention, a current output circuit is provided which comprises: a plurality of current mirror circuits, each of the current mirror circuits including a pair of MOS transistors with gate electrodes being connected in common, and a main electrode of one of the pair of MOS transistors being connected to a current output terminal; a plurality of hold capacitors each connected to the gate electrodes of the current mirror circuit; a reference current source being selectively connected to the other of the pair of MOS transistors of the current mirror circuit; and an operational amplifier whose output terminal is selectively connected to the gate electrodes of each selected current mirror circuit and whose one of a pair of input terminals is connected to a main electrode of the other of the pair of MOS transistors of each selected current mirror circuit, to form a feedback loop.
The current output circuit may further comprises: a sampling switch for selectively connecting the reference current source to the main electrode of the other of the pair of MO

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