Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-06-09
2002-10-22
Sherry, Michael (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB
Reexamination Certificate
active
06469538
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is generally directed to a current monitoring circuit and, more specifically, to a circuit capable of detecting a latchup condition or other over-current condition using a magnetic field detection transistor (or magFET).
BACKGROUND OF THE INVENTION
The power and complexity of integrated circuits, such as microprocessor chips, random access memory (RAM) chips, application specific integrated circuit (ASIC) chips, and the like, has increased dramatically in the last twenty years. This complexity has increased the likelihood of a manufacturing defect occurring on the chip. It also has increased the likelihood that a poor chip design may make the integrated circuit more susceptible to error conditions, such as latch-up, during times when the integrated circuit is operating under adverse conditions, such as high noise, power supply over-voltage conditions, high temperature, and the like. A common technique for screening integrated circuits (IC) is to measure the I
DDQ
of an integrated circuit under test. I
DDQ
is the power supply current in a quiescent operating condition. Faulty integrated circuits have a different I
DDQ
signature compared to non-faulty integrated circuits.
To increase the reliability of integrated circuits and to detect error conditions and defective chips more rapidly, it is common practice to incorporate built-in self test (BIST) circuitry in many types of integrated circuits. However, adding built-in self test circuitry presents additional problems. As the level of sophistication of self-testing increases, so does the size and complexity of the BIST circuitry. This results in a tradeoff between silicon area and detection sensitivity. Furthermore, the BIST circuitry itself may cause errors. This is particularly true as the complexity of the BIST circuitry increases. Finally, it is essential that the built-in self test (BIST) circuitry be able to monitor voltages and currents in an integrated circuit without interfering with the operation of the circuits that are being tested.
Therefore, there is a need in the art for improved circuitry for detecting error conditions in integrated circuits. In particular, there is a need in the art for built-in self test (BIST) circuitry that is simple and reliable and yet capable of performing relatively complex and sensitive testing. More particularly, there is a need in the art for BIST circuitry that is capable of accurately and non-intrusively monitoring current levels in an integrated circuit.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide an apparatus for monitoring a load current drawn by an electrical circuit in a wire. In an advantageous embodiment of the present invention, the apparatus comprises: 1) a Lorentz force MOS transistor having a first drain current (ID
1
) and a second drain current (ID
2
), wherein the Lorentz force MOS transistor is disposed proximate the wire carrying the load current and wherein a magnetic force generated by the load current increases a first current difference between the first drain current and the second drain current; and 2) a current difference amplification circuit capable of detecting the first current difference between the first drain current and the second drain current and generating an amplified output signal.
According to one embodiment of the present invention, the apparatus further comprises a current monitoring circuit coupled to the current difference amplification circuit capable of detecting and measuring the amplified output signal.
According to another embodiment of the present invention, the current monitoring circuit compares the amplified output signal to a predetermined threshold level and generates an error signal if the amplified output signal exceeds the predetermined threshold level.
According to still another embodiment of the present invention, the apparatus further comprises a switch controlled by the current monitoring circuit capable of coupling the wire to a power supply.
According to yet another embodiment of the present invention, the current monitoring circuit opens the switch and measures the amplified output signal when the load current is zero to thereby determine an initial current difference reference.
According to a further embodiment of the present invention, the current monitoring circuit closes the switch and measures the amplified output signal to determine the first current difference.
According to a still further embodiment of the present invention, the Lorentz force MOS transistor is disposed within a loop formed by the wire.
According to a yet further embodiment of the present invention, the Lorentz force MOS transistor is disposed within a plurality of concentric loops formed by the wire.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.
REFERENCES:
patent: 5438990 (1995-08-01), Wahlstrand et al.
patent: 5489846 (1996-02-01), Li et al.
patent: 5801533 (1998-09-01), Kalb, Jr.
patent: 6051441 (2000-04-01), McDowell et al.
Jorgenson Lisa K.
Munck William A.
Sherry Michael
STMicroelectronics Inc.
Tang Minh N.
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