Current-mode sense amplifier with low power consumption

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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Reexamination Certificate

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06449191

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a current-mode sense amplifier used in a flash memory, and more specifically, the present invention discloses a current-mode sense amplifier with lower power consumption operated under low supply voltage.
2. Description of the Prior Art
In recent years, technology and applications of flash memory have gradually been developed along with requirements of portable electronic products. These portable electronic products comprise film of a digital camera, a handheld electric device, a memory of a video game apparatus, a personal digital assistant (PDA), a telephone recorder, and a programmable IC, etc. Flash memory is a non-volatile memory, in which an operating principle is to control a switch of a gate channel to achieve an objective of memorizing data via changing a threshold voltage of a transistor or a memory cell so as to prevent data stored in the memory from disappearing due to disconnection with a power supply.
In general, the flash memory mainly comprises a floating gate for storing electric charges, and a control gate disposed on the floating gate for controlling access of data, where the control gate is separated from the floating gate via a dielectric layer formed by an oxide-nitride-oxide (ONO) structure. Therefore, the memory can utilize a principle of thermal electrons or tunneling to store induced electric charges within the overlapped gates so as to store a signal “0” in the memory. If data stored in the memory needs be changed, the only process is to supply a small extra amount of energy to remove electrons stored in the floating gate so as to rewrite data.
To access states of each memory cell in the memory, a sense amplifier is used to detect the induced electric charges stored in the memory cells so as to determine a value “0” or “1” that the memory cells represent. In general, the sense amplifier divides into a voltage mode and a current mode according to detecting types. For example, when a flash memory operates under a low voltage, the sense amplifier with the voltage mode cannot operate normally in such low voltage situations due to lower voltage swings. Therefore, the sense amplifier cannot exactly determine the storing state of the induced charges stored in the memory cells. Nevertheless, the sense amplifier using the current mode can be operated in the flash memory under the low voltage. The sense amplifier can obtain the storing state of the induced electric charges stored in the memory cells through an influence of current variance vs. voltage.
Please refer to FIG.
1
.
FIG. 1
is a circuit diagram of a current-mode sense amplifier
10
of a flash memory according to the prior art. The sense amplifier
10
comprises a signal generator
11
for inputting pulses, an output terminal
13
for outputting signals displayed in binary digits, two input circuits
12
and
14
respectively connected to a reference cell
16
and a memory cell
18
, a differential amplifier
20
for generating an output signal according to two different input signals, a voltage source Vdd for providing operating bias voltage of the sense amplifier
10
, and another differential amplifier
22
for processing currents outputted from the reference cell
16
and the memory cell
18
and generating corresponding voltage variance at two terminals A and B.
The input circuits
12
and
14
both comprise two control switches S
1
and S
2
for controlling on/off states of the input circuits
12
and
14
. A transistor
24
and a transistor
26
of the differential amplifier
22
form a current mirror. Therefore, a current flowing out of the reference cell
16
generates a current with the same value in the differential amplifier
22
via flowing through the current mirror. Similarly, a transistor
28
and a transistor
30
of the differential amplifier
22
also form a current mirror. Therefore, a current flowing out of the memory cell
18
generates a current with the same value in the differential amplifier
22
via flowing through the current mirror.
If the voltage source Vdd provides 1.8 volts functioning as the operating bias voltage, and when the signal generator
11
inputs a signal that is at a high voltage level, the transistors
32
and
34
are on. Therefore, voltages of terminals A and B will approach ground voltage so that an output voltage generated from the differential amplifier
20
will reset to the ground voltage due to the equal voltage between the two terminals A and B.
When the signal generator
11
inputs at a low voltage level, the transistors
32
and
34
are off. Furthermore, when the control switches S
1
and S
2
are on and the input circuits
12
and
14
are thus formed passageways, the current flowing out of the input circuit
12
will flow into the differential amplifier
22
via passing through the current mirror formed by the transistors
26
and
24
. Similarly, the current flowing out of the input circuit
14
will flow into the differential amplifier
22
via passing through the current mirror formed by the transistors
28
and
30
.
If the current generated from the input circuit
12
is smaller than the current generated from the input circuit
14
, an increasing rate of the voltage at terminal A will be larger than increasing rate of the voltage at terminal B. Therefore, when the voltage at terminal A reaches a threshold value so as to switch a transistor
33
on, the voltage at terminal B still does not reach a threshold value of a transistor
35
yet. Then, the transistor
33
will be on so as to decrease the voltage at terminal B and to be limited under the ground voltage, and the transistor
35
remains in a closed state so as to cause the voltage of terminal A to be larger than the voltage of terminal B. Finally, the differential amplifier
20
enhancing the voltage swing will generate an output voltage, which is near to that of the voltage source Vdd.
Similarly, if the current generated from the input circuit
12
is larger than the current generated from the input circuit
14
, the differential amplifier
20
will generate an output voltage that is near to the ground voltage. When the sense amplifier
10
operates, terminals A and B use the ground voltage functioning as the threshold value to be smoothly increased. When the transistor
32
or
34
reaches the threshold value, one end of terminals A and B will be limited by the ground voltage and be decreased.
The other terminal of terminals A and B must continuously provide current so as to increase the voltage to approach the voltage source Vdd. Therefore, the prior current-mode sense amplifier
10
needs more energy to operate, thus power consumption of the sense amplifier
10
is larger.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide a current-mode sense amplifier of a flash memory for operating in a low-voltage situation so as to consume less power to solve the aforementioned problems.
The claimed invention, briefly summarized, discloses a current-mode sense amplifier for detecting data stored in a flash memory cell. The sense amplifier has a first current generator for generating a first current to a first circuit according to current flowing out of the memory cell, a second current generator for generating a second current to a second circuit according to current flowing out of a reference cell, and a switch. When the switch is on and a common node of the first circuit and the second circuit is floating, the first and second circuits will generate equal initial voltages. When the switch is off and the common node of the first and second circuits is grounded, one of the initial voltages will increase, and the other initial voltage will decrease.
It is an advantage of the claimed invention that before the claimed current-mode sense amplifier of the flash memory initiates the output circuit to detect currents of the memory cell and the reference cell, electric potential of two terminals of the output circuit will be increased to a predetermined level. Then, when

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