Current mode sample-and-hold circuit

Details Current mode sample-and-hold circuit Current mode sample-and-hold circuit

1991-09-16

1993-07-13

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307491, 307494, G11C 2702

Patent

active

052276767

ABSTRACT:
The current mode sample-and-hold circuit includes a differential amplifier having a non-inverting input coupled to a first leg of a current mirror from which a first current to be sampled is drawn. An inverting input of the differential amplifier is coupled to its output and further coupled to a capacitor through a sample hold switch. The first current drawn from the first leg of the current mirror causes the capacitor to charge, through the differential amplifier. The charged capacitor is coupled to the current mirror and biases the current mirror so as to provide the required first current. Opening the sample hold switch causes the capacitor to maintain a bias level determined by the first current. The bias signal in turn causes a mirrored current flowing in a second leg of the current mirror to be maintained, even in the absence of the first current. Thus an input current is sampled and a corresponding output current is provided. The capacitor operates in a feedback loop for improving accuracy. Furthermore, the capacitor is isolated from both the input and output providing high frequency capability. Alternatively, the sample hold switch may be replaced by a diode for providing a peak detector function.

REFERENCES:
patent: 3469112 (1969-09-01), Hands et al.
patent: 3643110 (1972-02-01), Thompson
patent: 4185211 (1980-01-01), Kucharewski
patent: 4321488 (1982-03-01), Srivastava
patent: 5004935 (1991-04-01), Murayama et al.
patent: 5012133 (1991-04-01), Hughes
patent: 5109169 (1992-04-01), Hughes
W. D. Pricer, "Blur Correction Circuit for Scanners" IBM Technical Disclosure Bulletin, vol. 17, No. 12, May 1975 pp. 3545-3547.

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