Current-mode pipelined ADC with time-interleaved sampling and mi

Details Current-mode pipelined ADC with time-interleaved sampling and mi Current-mode pipelined ADC with time-interleaved sampling and mi

1997-04-29

1999-11-23

Williams, Howard L.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341156, H03M 144, H03M 114

Patent

active

059908203

ABSTRACT:
To convert an analog current to a digital signal using a high-speed pipelined analog-to-digigal (A/D) converter, the A/D converter may comprise a current sample- and hold (S/H) circuit at the input and several identical pipelined stages, where each stage contains a current S/H circuit, a current interstage low-resolution A/D converter and current references. To improve the speed of pipelined current-mode A/D converters the capacitive load seen by the output of every stage will be reduced. By adjusting the reference currents the power consumption will also be reduced. It is possible to achieve about 100 Msamples/s conversion rate and to reduce the power consumption by several times compared with existing designs. To increase the operation speed and to provide means to reduce the power consumption the pipelined current-mode A/D converter may comprise an S/H circuit (7) as the input and N pipelined stages (8), each of which contains an internal low-resolution A/D converter (9), a D/A converter (10), an S/H circuit (11), a reference current source (12) and an adder/subtractor (13). The most distinguishing features of the invented architecture are: 1) the inputs to the internal A/D converter and the interstage S/H circuit are timeinterleaved; and 2) the reference current to the D/A converter in every stage can be different.

REFERENCES:
patent: 4684924 (1987-08-01), Wood
patent: 4894657 (1990-01-01), Hwang et al.
patent: 5043732 (1991-08-01), Robertson et al.
Gustavsson et al., New Current-Mode Pipeline A/D Converter Architectures, 1997 IEEE International Symposium on Circuits and Systems Jun. 9-12, 1997, pp. 417-420.
Wong et al. Current-Mode Cyclic A/D Conversion Technique, Electronics Letters, Feb. 4, 1993 vol. 29, No. 3, pp. 249-250.
IEEE Journal of Solid-State Circuits, vol. 30, No. 5, May 1995, Chung-Yu Wu et al., "A CMOS Transistor-Only 8-b 4.5 Ms/s Pipelined Analog-to-Digital Converter Using Fully-Differential Current-Mode Circuit Techniques", pp. 523-532.
IEE Circuits and Systems Series 2, Toumazou, C. et al., "Analogue IC design: the current-mode approach," pp. 491-503.
IEE Circuits and Systems Series 5, Toumazou, C. et al., "Switched-Currents an analogue technique for digital technology," pp. 304-322.

Affiliated with

Also associated with

Rating

Current-mode pipelined ADC with time-interleaved sampling and mi does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Current-mode pipelined ADC with time-interleaved sampling and mi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Current-mode pipelined ADC with time-interleaved sampling and mi will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1226657