Current-mode multi-valued full adder in semiconductor device

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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C708S493000

Reexamination Certificate

active

07155474

ABSTRACT:
A full adder in a semiconductor device, includes a reference current generation unit for generating a reference current, a carry generation unit for generating a threshold current for generating a carry in response to the reference current and for generating the carry by comparing the input current and the threshold current in response to an input current and a sum signal generation unit for outputting a differential sum signal for the input current and the threshold current according to a comparison result of the carry generation unit.

REFERENCES:
patent: 4215418 (1980-07-01), Muramatsu
patent: 4982356 (1991-01-01), Ando
patent: 5175703 (1992-12-01), Ong
patent: 1999-022762 (1999-03-01), None
patent: 1999-0074561 (1999-10-01), None
patent: WO 96/42049 (1996-12-01), None
Current, “Current-Mode CMOS Multiple-Valued Logic Circuits”, IEEE Journal of Solid-State Circuits, Vo. 29, No. 2, Feb. 1994, pp. 95-107.
“Design of Full-Adder Using Current-Mode Multiple-Valued Logic MOS Circuis” (Journal of The Institute of Electronics Engineers of Korea, vol. 39-SD, No. 1, Jan. 2002).
Korean Dec. 12, 2003 office action in connection with Koren application No. 2002-25757.

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