Current mode binary/BCD arithmetic logic unit with parity

Details Current mode binary/BCD arithmetic logic unit with parity Current mode binary/BCD arithmetic logic unit with parity

1977-01-03

1978-03-14

Malzahn, David H.

Boots, shoes, and leggings

G06F 1110

Patent

active

040794571

ABSTRACT:
An improved binary/binary coded decimal arithmetic logic unit employing soft-saturating current mode logic gates operates on pure binary data or binary coded decimal (BCD) data. The unit performs 16 binary and 2 decimal arithmetic operations and 16 Boolean operations on two 4-bit plus parity input fields. The particular operation is determined by a 5-bit mode control signal. A carry-in input CIN, duplicate carry-in input CIND, parity check PCK input, invert parity input IP, decimal mode signal D, and decimal add input DA are also provided. The device generates a binary output resultant of the operation defined by the mode control signal. In addition to the arithmetic or logic operations, the unit performs parity checking, parity carry, and parity prediction operations on 4-bit plus parity binary and BCD fields.

REFERENCES:
patent: 3758760 (1973-09-01), Cowan
patent: 3925647 (1975-12-01), Louie
patent: 3958112 (1976-05-01), Miller
patent: 3986015 (1976-10-01), Gooding
Hsiao & Wolff, "High-Speed, Self-Checked, BCD Adder" IBM Tech. Disclosure Bulletin, vol. 14, No. 12, May 1962, pp. 59-61.

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