Current mode arithmetic logic circuit with parity prediction and

Details Current mode arithmetic logic circuit with parity prediction and Current mode arithmetic logic circuit with parity prediction and

1977-01-03

1978-04-11

Atkinson, Charles E.

Boots, shoes, and leggings

G06F 1110

Patent

active

040842533

ABSTRACT:
A current mode arithmetic logic circuit utilizes a unique combination of a 4-bit and a 5-bit arithmetic logic unit for performing parity prediction and parity checking on an n-bit byte plus parity, in addition to performing 16 binary or 16 Boolean operations on two n-bit plus parity bytes.

REFERENCES:
patent: 3649817 (1972-03-01), Keller et al.
patent: 3758760 (1973-09-01), Cowan
patent: 3925647 (1975-12-01), Louie
patent: 3986015 (1976-10-01), Gooding et al.
Hsiao and Wolff, High-Speed, Self-Checked, BCD Adder, IBM Technical Disclosure Bulletin, vol. 4, No. 12, May 1962, pp. 59-61.

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