Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit
Reexamination Certificate
2001-10-26
2004-02-17
Le, Que T. (Department: 2878)
Radiant energy
Photocells; circuits and apparatus
Photocell controlled circuit
C250S2140RC
Reexamination Certificate
active
06693270
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to multiplexing analog signals onto a common bus and, more particularly, to a current mode analog video bus for a device, such as an imager, and a method thereof
BACKGROUND OF THE INVENTION
Modern, solid-state, visible light imaging devices have found their way into a variety of consumer, scientific, industrial, medical and military cameras over the last thirty years or so. (These devices include the entire class of solid-state, silicon, visible light imagers including charge coupled devices (CCD's), charge injection devices (CID's) and CMOS imagers.) Over this period of time, these devices have exhibited several important trends that have only accelerated in the past decade and are discussed below.
One trend is towards increasing the size of the image array (i.e. total number of pixels per frame). This trend towards larger arrays is driven by new application requirements, the increasing prevalence of computers, and the increasing resolution of electronic displays. This trend has been enabled by advances in integrated circuit fabrication technology.
Another trend is towards increasing the number of frames per second. This trend is especially true for industrial and scientific applications where high throughput and transient event capture are key areas of concern.
Another trend is towards higher levels of integration on the image chip itself. The industry is in the early stages of having a camera on an image chip. As early as 1991, university researchers in Scotland were reporting work on a 312 by 287 pixel ‘single-chip camera’, as disclosed in “Video Image On a Chip”, David Scott, Popular Science, September 1991, which is herein incorporated by reference. This trend toward system level integration on to a single chip is driven by cost, a desire for smaller devices, and the expanding markets for digital imagers. Again, this trend has been enabled by advances in fabrication technology, specifically the drive toward smaller minimum feature sizes.
Another trend is towards lower power. This trend is driven by the increasing demand for digital still cameras and digital video cameras which rely on batteries for power. This particular trend reflects a trend in electronics generally.
Another similar trend is towards lower voltage. As fabrication technologies tend toward smaller feature sizes, the devices can withstand lower and lower voltages. As a result, it is only a matter of time before the supply voltages drop from the now common 5 volts for 0.5 &mgr;m CMOS technology to 2.5 volts and then 1.0 volt for the next generation technologies.
Yet another trend is towards lower cost. This trend goes hand-in-hand with higher levels of integration and is a driver for decreases in process feature size.
Yet another trend is towards application ease. This trend is less obvious than the others discussed above, but is a natural extension of increasing levels of integration. As circuits become more dense and camera functions are more readily available as part of the imager, the ease of designing a camera with a modem imager becomes much easier.
One of the problems created by a combination of these trends is with analog bandwidth. More specifically, the trend toward larger arrays (i.e. more pixels per frame) and higher frame rates requires that the video output bandwidth, or pixels per second, increase proportionately. For example, a small, relatively slow imager having a resolution of 256×256 and a frame rate of 10 frames per second need only produce video at greater than 0.66 Mpixels per second. However, a modern mega-pixel imager for industrial or medical applications might have a resolution of 1,024×1,024 and a frame rate of 60 frames per second. Such a camera would need to produce video at 70-80 Mpixels per second (depending on overhead). Many existing devices cannot readily achieve these high analog video bandwidths through a single analog output port and so compromises must be made. As such, depending on the camera design constraints, the analog bandwidth limitation of the imaging device represents an upper limit on array size, frame rate or both.
Most mega-pixel image sensors, including both CCD imagers and Active Pixel Sensor (APS) type CMOS imagers, have a maximum pixel rate inadequate to meet the frame rate needs of higher end applications, such as for industrial and scientific and high definition television (HDTV) imaging applications. With respect to CCD imagers, these imagers are limited by both clocking rates and the speeds of the Correlated Double Sampling (CDS) circuitry. Additionally, the higher amplifier bandwidth required for high pixel rates for these mega pixel image sensors results in increased levels of noise. With respect to the column parallel nature of CMOS imagers, the amplifier and CDS in these imagers can be run at the line rate, rather than the pixel rate, which is generally much easier to achieve. However, the video bandwidth constraints for CMOS imagers come in terms of the multiplexing speed. CMOS imagers typically multiplex their column signals onto a common analog video bus in a sequential fashion. The more columns that are multiplexed or switched onto the bus, the greater the capacitive load that the bus presents to each column amplifier. Therefore, as more columns are connected to the bus, the bandwidth of the bus is reduced. Alternatively, greater power is needed to charge and discharge the bus with its associated capacitance to maintain bandwidth.
One example of a common video bus with a distributed capacitive load associated with each individual column switch is illustrated in FIG.
1
. In order for each amplifier
100
to accurately transfer the pixel value from the array
101
represented by a voltage signal onto the common video bus
102
, each amplifier
100
must charge or discharge the bus
102
within one pixel time constant. The voltage signal must be stable long enough for a sample and hold circuit (or similar) to accurately present the resultant signal to an analog to digital converter (ADC) (not shown). Typically, at least 5&tgr; (tau or time constants) are needed to accurately allow the common video bus
102
to settle the voltage signal presented by each individual column amplifier
100
.
At higher video bus speeds the individual column amplifier
100
is unable to properly charge or discharge the common video bus
102
resulting in a loss of amplitude which is perceived as a loss of contrast ratio in the video image. At higher pixel element rates where the contrast ratio is compromised, the individual column amplifier characteristic and the video switch characteristics begin to affect the resultant video. The individual column amplifiers
100
will have slightly different offsets with slightly different drive capabilities and each video switch will have slightly different resistances and slightly different thresholds. This combination of column amplifier and video switch characteristics results in each column amplifier having different time constants relative to charging and discharging the video bus. The column amplifier and video switch are common to every pixel in that column. Thus, variations in the video switch characteristics result in what appears to be column based Fixed Pattern Noise (FPN). As more columns are added, each video switch adds more associated capacitance due to the source and drain junctions of MOSFET transistors (or due to the corresponding junctions of bipolar transistors).
In order to overcome the constraints, some designers of CCD's and APS sensors have resorted to dividing up an imager
104
into halves, quarters
104
(
1
)-
104
(
4
), or smaller groupings of sub-imagers, jammed together, as shown in FIG.
2
. The signals from each of these sub-imagers
104
(
1
)-
104
(
4
) is brought out to its own output port
106
(
1
)-
106
(
4
). This approach has been used to provide high frame rate devices, or even to meet standard frame rates with large mega-pixel imagers. In essence, it allows each port
106
(
1
)-
106
(
4
) to operate at its
Iodice Robert
Pace Matthew
Zarnowski Jeffrey
Le Que T.
Molldrem, Jr. Bernhard P.
Silicon Video, Inc.
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