Current mode 5-bit arithmetic logic unit with parity

Details Current mode 5-bit arithmetic logic unit with parity Current mode 5-bit arithmetic logic unit with parity

1977-01-03

1978-04-11

Atkinson, Charles E.

Boots, shoes, and leggings

G06F 1110

Patent

active

040842525

ABSTRACT:
An arithmetic logic unit employing soft-saturating current mode logic gates receives as inputs two 5-bit bytes and generates a 5-bit binary output byte in accordance with the particular operational mode prescribed by a mode control signal. The unit performs sixteen binary arithmetic or sixteen Boolean logic operations on two 5-bit input fields Ai and Bi. A carry-in input CIN, a carry generate output G, and a carry propogate output P are provided so that the device can be utilized in a full carry look-ahead configuration with a separate carry look-ahead array. A special output F= is provided for zero detection purposes. In addition to the arithmetic or logic operations, the unit generates a parity of the half-sums signal HS, a parity of the half-parities signal HP, a parity of the carries signal PC, and a carry error signal CE. A carry-out signal COUT is also generated.

REFERENCES:
patent: 3649817 (1972-03-01), Keller et al.
patent: 3758760 (1973-09-01), Cowan
patent: 3925647 (1975-12-01), Louie
patent: 3986015 (1976-10-01), Gooding et al.
Hsiao and Wolff, High-Speed, Self-Checked, BCD Adder, IBM Technical Disclosure Bulletin, vol. 4, No. 12, May 1962, pp. 59-61.

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