Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2002-01-14
2002-11-19
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S051000
Reexamination Certificate
active
06483352
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 90123429, filed Sep. 24, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a sense amplifier, and more particularly, to a current mirror sense amplifier.
2. Description of the Related Art
In the conventional sense amplifier structure, a differential amplifier is used for comparison to obtain data 1 or data 0. However, in the sense process, a sufficient time span has to be reserved for the first section, the pre-charge time. When a bit line overcharge occurs in the pre-charging process or a weak pre-charge is used, the detection of data
1
becomes slow, and the pre-charge process takes much time for pre-charging bit lines. To increase the speed of data transient without being affected by noise, one has to alter the pre-charge control.
FIG. 1
shows a conventional first type sense amplifier. The operation method of the conventional sense amplifier uses a first transistor
112
as a diode to convert a current of a selected memory cell into its corresponding voltage (VC). Using a differential amplifier, the corresponding voltage VC is compared to a reference voltage VREF to obtain the data 0 and 1.
However, a sense amplifier requires 1 differential amplifier, and Each of 2-8 sense amplifiers need a reference voltage generator such that a larger current is utilized and die size becomes relatively large. Plus, because the variation of the corresponding voltage (VC) is smaller, the noise margin of data 0 and 1 is poor.
Therefore, a second type sense amplifier that does not require a differential amplifier has been developed. The second type sense amplifier is smaller in circuit design. Referring to
FIG. 2
, it uses a clock signal CK
1
for pre-charge, so that N
1
can be pre-charged to the level of data 0. When the clock signal CK
1
becomes high level, the data level can be obtained at N
1
according to the discharge result of the bit line. The inverter
234
is used as a delay for bit line discharge. Passing through the delay
234
, the data is stored by the latch
235
formed of the inverters
222
and
223
.
This kind of amplifier still has a lot of problems. For example, the speed for converting data 0 to 1 is determined by the speed for the N
1
node of the selected memory cell discharging a current, and thus the current of the N
1
node becomes in a state of a low level. Therefore, it is not suitable for high speed apparatus, and during a pre-charge cycle, a strong pre-charge efficiency causes a bit line to overshoot; a weak pre-charge efficiency causes failure of data access.
According to the above, in the conventional sense amplifier, the speed of data access is affected by the pre-charge time.
SUMMARY OF THE INVENTION
The invention provides a sense amplifier that does not have to reserve a pre-charge time span. Such a sense amplifier is not affected by the pre-charge time, so that the data can be applied to high-speed transient apparatus.
The invention provides a current mirror sense amplifier including a two stage current mirror, a first transistor and a second transistor.
The first and second transistors each have a first and second connection terminal. The first transistor has a gate electrically connected to a pre-charge voltage. The first connection terminal of the first transistor is electrically connected to a power source. A gate of the second transistor is electrically connected to a reference signal. The first connection terminal of the second transistor is electrically connected to the above power source. The first connection terminals of the first and the second transistors are connected to the current output terminal of the two-stage current mirror in parallel.
In one embodiment of the invention, the two-stage current mirror comprises a third transistor, a fourth transistor, a fifth transistor and a sixth transistor. The third transistor has a gate, a first connection terminal and a second connection terminal. The first connection terminal of the third transistor is coupled to the power source. The fourth transistor has a gate, a first connection terminal and a second connection terminal. The first connection terminal of the fourth transistor is coupled to the power source. The fifth transistor has a gate, a first connection terminal and a second connection terminal. The first connection terminal of the fifth transistor is coupled to ground. The sixth transistor has a gate, a first connection terminal and a second connection terminal. The first connection terminal of the sixth transistor is coupled to ground.
The gate and the second connection terminal of the third transistor, and the gate of the fourth transistor are coupled to one node, which is the current input terminal of the two-stage current mirror. The second connections of the fourth and fifth transistors, and the gates of the fifth and sixth transistor are coupled to a node. The second connection terminal of the sixth transistor is the current output terminal of the two-stage current mirror.
The third transistor and the fourth transistor construct a first stage current mirror, while the fifth and sixth transistors construct a second stage current mirror.
When the current mirror starts sensing current, the current enters from the current input terminal of the current mirror. By changing the width-length ratio (W/L) of the second transistor, the current ratio between the output terminal of the current mirror and the second connection terminal of the second transistor is changed. That is, the current ratio between the second connection terminal of the sixth transistor and the second connection terminal of the second transistor is changed. After being sensed, the first transistor provides a current to the current output terminal of the current mirror to change the level thereof
The two-stage current mirror of the sense amplifier steadily amplifies the current input from the current input terminal at the current output terminal. A set of parallel connected transistors in the amplifier prevents the voltage at the output terminal from dropping too low due to pre-charging current during the sense process of the current mirror. The effect caused by noise can also be suppressed.
In addition, the loading of the output terminal is far less than that of the input terminal. Therefore, the charge/discharge speed at the output terminal is much faster than that of the input terminal. As a result, the data access speed at the output terminal is not slowed down due to the loading of the input terminal.
According to the above, the invention uses a two-stage current mirror for the data level sense. The current from input terminal is steadily amplified via the two-level current mirror. Using a set of parallel connected transistors, a level is provided to compensate the voltage drop at the output terminal caused by pre-charging current during the sense process of the amplifier. Thus, the data can be steadily applied to a high transient speed apparatus without being affected by pre-charging time.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 5355038 (1994-10-01), Hui
patent: 5369614 (1994-11-01), Miyanishi
patent: 5929658 (1999-07-01), Cheung et al.
patent: 5986937 (1999-11-01), Yero
patent: 6141246 (2000-10-01), Derman et al.
patent: 6362661 (2002-03-01), Park
Chen Ti-Wen
Kuo Sheng-Chang
J.C. Patents
Macronix International Co. Ltd.
Tran Toan
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