Current mirror circuit employing depletion mode FETs

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307450, 307264, 307546, 307547, 307548, H03K 1716

Patent

active

051665530

ABSTRACT:
A semiconductor circuit including first and second FET's for delivering an output signal without being affected by a change in threshold voltage of the FET's is disclosed. According to one practical form of the semiconductor circuit, the drain-source current path of an additional FET whose gate and source are shorted to each other, is connected in parallel to the drain-source current path of the first FET whose gate and drain are shorted to each other, to make the voltage-current characteristic of the second FET agree with that of the parallel combination of the first and additional FET's. According to another practical form of the semiconductor circuit, a voltage dividing circuit is connected in parallel to the drain-source current path of the first FET, and a divided output voltage from the voltage dividing circuit is applied between the gate and source of each of the first and second FET's.

REFERENCES:
patent: 4926071 (1990-05-01), MacMillan et al.
Conf. on Solid State devices, Tokyo, 1974, "Logic Circuits with Zum Gate Schottky Barrier FETs" Suzuki et al., pp. 219-224.
"Analysis and Design of Analog Integrated Circuit" Zud ed. (1984), John Wiley & Sons, Inc. pp. 709-718.

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