Current mirror circuit and charge pump circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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Details

C327S053000, C327S060000

Reexamination Certificate

active

06177827

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a current mirror circuit for generating a current which is in a constant ratio to a reference current.
2. Description of the Background Art
In general, semiconductor integrated circuits often employ a current mirror circuit for generation of a current which is in a constant ratio to a reference current (including a current equivalent to the reference current).
FIG. 6
is a circuit diagram illustrating the construction of a current mirror circuit CM
2
. The current mirror circuit CM
2
comprises two N-channel MOS transistors T
1
and T
2
having sources connected to each other and gates connected to each other, with the drain of the N-channel MOS transistor T
1
connected to the gate thereof.
In the current mirror circuit CM
2
, since the N-channel MOS transistors T
1
and T
2
are at the same gate potential, a reference current Iref supplied to the drain of the N-channel MOS transistor T
1
provides a constant ratio of the value of the reference current Iref to the value of a current Iout flowing between the drain and source of the N-channel MOS transistor T
2
. This ratio may be controlled depending on a size ratio between the N-channel MOS transistors T
1
and T
2
.
The current mirror circuit CM
2
, of course, may employ P-channel MOS transistors. Also, bipolar transistors may be used in place of the MOS transistors, in which case the sources, drains and gates of the above described MOS transistors should be replaced with emitters, collectors and bases, respectively, for connections therebetween. In such cases, similar size adjustment may be made to generate the current Iout which is in a constant ratio to the reference current Iref.
Such a current mirror circuit is based on the precondition that it operates in a so-called constant current region (referred to as a saturated region for a MOS transistor or as an unsaturated region for a bipolar transistor) which is found in the relationship between a drain-source voltage and a drain-source current for a MOS transistor or the relationship between a collector-emitter voltage and a collector-emitter current for a bipolar transistor.
Unfortunately, the bipolar transistor presents the problem of the Early effect such that the increase in a base-collector voltage changes the width of a depletion layer between the base and the collector to change a substantial base layer width. As the collector-emitter voltage increases, the collector-emitter current is not constant but slightly increases because of the Early effect. Thus, the change in the collector-emitter voltage causes the change in the collector-emitter current even in the so-called constant current region, although a base-emitter current is constant.
Similarly, also in the MOS transistor, as the drain-source voltage increases, the drain-source current is not constant but slightly increases even if a gate-source voltage is constant. This results from the change in a channel length and is described using a value known as a channel length modulation parameter.
For this reason, for example, in the above described current mirror circuit CM
2
, when the drain-source voltage of the N-channel MOS transistor T
2
varies, the value of the output current Iout is changed. This might fail to provide the constant ratio between the value of the reference current Iref and the value of the output current Iout which should be determined only by the transistor size ratio.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a current mirror circuit comprises: an output terminal; a first transistor having a first current electrode, a second current electrode, and a control electrode connected to the first current electrode, there being a flow of a reference current between the first and second current electrodes; a second transistor having a first current electrode connected to the output terminal, a second current electrode connected to the second current electrode of the first transistor, and a control electrode connected to the control electrode of the first transistor; a third transistor having a first current electrode, a second current electrode connected to the second current electrode of the first transistor, and a control electrode connected to the output terminal, there being a flow of a predetermined current between the first and second current electrodes of the third transistor; and a first constant current source connected to the second current electrode of the first transistor.
According to a second aspect of the present invention, a charge pump circuit comprises: an output terminal; a first transistor having a first current electrode, a second current electrode, and a control electrode connected to the first current electrode, there being a flow of a reference current between the first and second current electrodes; a second transistor having a first current electrode connected to the output terminal, a second current electrode connected to the second current electrode of the first transistor, and a control electrode connected to the control electrode of the first transistor; a third transistor having a first current electrode, a second current electrode connected to the second current electrode of the first transistor, and a control electrode connected to the output terminal, there being a flow of a predetermined current between the first and second current electrodes of the third transistor; a first constant current source connected to the second current electrode of the first transistor; a fourth transistor having a first current electrode connected to the output terminal, a second current electrode, and a control electrode; a first operational amplifier having a first input connected to the second current electrode of the fourth transistor, a second input receiving a reference potential, and an output connected to the control electrode of the fourth transistor; and a first filter receiving a first pulse signal for smoothing the first pulse signal to apply the smoothed first pulse signal to the second current electrode of the fourth transistor.
Preferably, according to a third aspect of the present invention, the charge pump circuit of the second aspect further comprises: a fifth transistor having a first current electrode connected to the first current electrode of the first transistor, a second current electrode, and a control electrode; a second operational amplifier having a first input connected to the second current electrode of the fifth transistor, a second input receiving the reference potential, and an output connected to the control electrode of the fifth transistor; and a second filter receiving a second pulse signal for smoothing the second pulse signal to apply the smoothed second pulse signal to the second current electrode of the fifth transistor.
In the current mirror circuit of the first aspect of the present invention, when the potential at the output terminal varies, the third transistor flows the current which increases/decreases depending on the variations in the potential at the output terminal, and the output current supplied from the second transistor to the output terminal is limited by the constant current. Therefore, the variations in the output current is suppressed.
In the charge pump circuit of the second aspect of the present invention, if the potential at the output terminal varies, the potential at the second current electrode of the fourth transistor is held stable by the negative feedback provided by the first operational amplifier. Thus, the fourth transistor can supply a substantially direct current having a value depending on the first pulse signal to the output terminal.
In the charge pump circuit of the third aspect of the present invention, the fifth transistor draws a substantially direct current having a value depending on the second pulse signal from the output terminal through the first and second transistors. Thus, a substantially direct current having a value depending on the difference between the first and second puls

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