Current mirror circuit

Details Current mirror circuit Current mirror circuit

1999-09-27

2001-03-06

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S530000, C323S315000

Reexamination Certificate

active

06198343

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to current mirror circuits, more particularly, current mirror circuits with a BiCMOS structure.
BACKGROUND OF THE INVENTION
Conventionally, current mirror circuits composed of MOS transistors are typically cascade connected to improve precision in the output current of the current mirror circuits.
For example, referring to the current mirror circuit section
104
shown in
FIG. 8
, in a first stage current mirror circuit, the gates of Pch MOS transistors P
101
and P
102
are connected to each other, and also to the drain of an MOS transistor P
101
. While a power source voltage V
cc
is applied to the sources of the two MOS transistors P
101
and P
102
, the drains thereof are connected to the respective sources of MOS transistors P
103
and P
104
that constitute a next stage current mirror circuit.
In addition, the gates of the two MOS transistors P
103
and P
104
are connected to each other, and further connected to the drain of the MOS transistor P
103
that serves as a current input terminal T
105
. Thus, as a predetermined current I
in
is supplied from a current source
105
via the current input terminal T
105
, the current mirror circuit section
104
is capable of producing an output current I
out
, of the same value as the current I
in
, flowing via the drain of the MOS transistor P
104
which serves as a current output terminal T
106
.
In the arrangement above, since the two current mirror circuits are cascade connected, the drain potentials of the MOS transistors P
101
and P
102
are both equal to the sum of the gate potential of the MOS transistors P
103
and P
104
and a threshold voltage V
th
, and are thereby equal to each other. As a result, current fluctuations caused by Early effect are restrained, and the precision of the output current I
out
can be improved.
Nevertheless, in the current mirror circuit section
104
in the arrangement, so as to allow each current mirror circuit to operate in the saturation region thereof, the gate-drain voltages of the MOS transistors P
101
to P
104
need to be held at a value not less than the threshold voltage V
th
. Therefore, the input and output voltage ranges of the current mirror circuit section
104
are limited from GND to V
cc
−2V
th
, where V
cc
is the power source voltage and GND is the ground level. Cascade connection narrows down the operating voltage range in this manner, which is an obstacle in lowering the voltage of the power source.
In order to widen the operating voltage range while maintaining the output precision of the current mirror circuit, Japanese Laid-Open Patent Application No. 6-104762/1994 (Tokukaihei 6-104762) and other documents disclose a current mirror circuit section
104
a
to which a bias voltage power source
106
is provided as shown in
FIG. 9
, for example. Pch MOS transistors P
111
and P
112
of which the gates are connected to each other, as well as Pch MOS transistors P
113
and P
114
of which the gates are connected to each other, are provided to the current mirror circuit section
104
a
, and the drain of the MOS transistor P
113
is connected to the gates of the MOS transistors P
111
and P
112
. Meanwhile, the gates of the MOS transistors P
113
and P
114
are both connected to the bias voltage power source
106
so that the MOS transistors P
111
to P
114
are fed with a voltage that allows the MOS transistors P
111
to P
114
to operate in the saturation regions thereof.
Note that, similarly to the case of the current mirror circuit section
104
shown in
FIG. 8
, the power source voltage V
cc
is applied to the sources of the two MOS transistors P
111
and P
112
; the drain of the MOS transistor P
111
is connected to the source of the MOS transistor P
113
; and the drain of the MOS transistor P
112
is connected to the source of the MOS transistor P
114
.
In the preceding arrangement, since the gate of the MOS transistor P
111
is connected to the drain of the MOS transistor P
113
, the input voltage range of the current mirror circuit section
104
a
is from GND to V
cc
−V
th
, thereby having become wider than that of the current mirror circuit section
104
shown in
FIG. 8
by a value equivalent to the threshold voltage V
th
. In addition, since the gate voltages of the two MOS transistors P
113
and P
114
are adjusted by the bias voltage power source
106
so that the MOS transistors P
111
to P
114
operate in the saturation regions thereof, the source voltages of the two MOS transistors P
113
and P
114
, i.e., the drain voltages of the two MOS transistors P
111
and P
112
, become equal to each other. As a result, the source-drain voltage Vds of the two MOS transistors P
111
and P
112
become equal to each other. Therefore, the precision of the output current I
out
can be relatively improved compared to use of a single current mirror circuit.
However, in the current mirror circuit section
104
a
having such an arrangement, if a variation in a property occurring during manufacture results in a difference (offset) in the gate lengths of the MOS transistors P
111
and P
112
, the offset degrades the precision of the output current I
out
.
More specifically, when the current mirror circuit section
104
a
is manufactured, non-uniformity occurring during wafer manufacturing causes in many cases differences in properties of the two MOS transistors P
111
and P
112
. Especially, for example, if there occurs a difference in threshold voltage V
th
due to a difference in gate length, one of the two MOS transistors P
111
and P
112
, which has a higher threshold voltage V
th
than the other, will generate a smaller current, and there occurs a difference between the input current I
in
, and the output current I
out
.
Here, if the gate lengths of the two MOS transistors P
111
and P
112
are specified to a large value, adverse effects of the offset can be reduced. Nevertheless, in such a case, the gate parasitic capacity of the two MOS transistors P
111
and P
112
increases. As a result, a new problem arises where feeding of the output current I
out
does not immediately takes place when the input current I
in
is introduced.
More specifically, when the input current I
in
is in an off state, the MOS transistors P
111
to P
114
are also maintained in an off state. Here, when the input current I
in
starts flowing, electric charges stored in the gate parasitic capacity of the two MOS transistors P
111
and P
112
are discharged, which reduces the gate voltage. Once a point is reached where the gate-source voltage V
gs
exceeds the threshold voltage V
th
(when the condition, V
gs
>V
th
, is satisfied), the two MOS transistors P
111
and P
112
conduct, and the output current I
out
changes into an on state. Here, since the gate lengths are specified to a large value to reduce the adverse effects of the offset, the gate parasitic capacity also has a large value. Therefore, feeding of the output current I
out
does not immediately takes place when the input current I
in
is introduced. As an example, if the gate parasitic capacity of the two MOS transistors P
111
and P
112
is 5 [pF], as shown in
FIG. 10
, feeding of the output current I
out
takes place about 1 [&mgr;s] after the input current I
in
of 5 [&mgr;A] is introduced.
Note that in a non-cascade-connected single current mirror circuit, the adverse effects of the offset of the two MOS transistors can be restrained by applying the power source voltage V
cc
to the sources of the two MOS transistors via resistors of the same resistance value. Nevertheless, in the conventional current mirror circuit section
104
a
shown in
FIG. 9
, if resistors are connected to the sources of the MOS transistors P
111
and P
112
, since the voltage drop across the resistor varies depending on the input current I
in
, the source voltages of the MOS transistors P
111
to P
114
fluctuates depending on the input current I
in
. As a result, the gate voltages of the MOS transistors P
113
and P
114
need to be either increased o

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