Current memory cell

Details Current memory cell Current memory cell

1992-04-20

1994-03-22

Sikes, William L.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307571, 307279, 307246, 323315, 365187, H03K 17687

Patent

active

052967522

ABSTRACT:
A current memory cell for sampling a current (I) at a current terminal (5) during a sample interval and for applying the current (I) to the current terminal (5) during a hold interval. A first switch (S1) connects a PMOS transistor (P1) as a diode during the sample interval and as a current source during the hold interval. During the sample interval the current in the current terminal (5) is mirrored to the PMOS transistor (P1). During the hold interval the current of the PMOS transistor is mirrored to the current terminal. The mirroring is effected by means of two NMOS transistors (N1, N2) and one reversing switch (S2), which reverses the input and output of the current mirror circuit between the sample intervals and the hold intervals. The current mirror circuit (N1, N2) and the PMOS current source (P1) collectively behave as a current sink which is insensitive to the substrate voltages which are caused by the body effect.

REFERENCES:
patent: 4958123 (1990-09-01), Hughes
patent: 5021692 (1991-06-01), Hughes
patent: 5023489 (1991-06-01), Macbeth
patent: 5028822 (1991-07-01), Hughes
patent: 5109169 (1992-04-01), Hughes
IEE Proceedings G. Electronic Circuits & Systems, vol. 137, No. 2, Apr. 1990, Stevenage GB, pp. 95-100, Wegmann Basic Principles of Accurate Dynamic Curent Mirrors.
Electronics Letters, vol. 26, No. 19, Sep. 1990, Enage GB pp. 1593-1595, Toumazou et al. High Performance Algorithmic Switched Current Memory Cell.

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