Current limiting technique for hybrid power MOSFET circuits

Details Current limiting technique for hybrid power MOSFET circuits Current limiting technique for hybrid power MOSFET circuits

2001-07-17

2003-04-22

Nguyen, Matthew (Department: 2838)

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific current responsive fault sensor

Reexamination Certificate

active

06552889

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor power switches. More particularly, the present invention relates to limiting the current in a power field effect transistor being used as a switch.
2. Related Art
Traditionally current limiting in a power switch has been done by a method called fold back current limiting. When using a FET as a power switch, the gate to source voltage (V
GS
) of the FET is the control voltage that is regulated in order to limit the FET drain current to a predefined level. The disadvantage of the fold back current limiting approach is that the voltage between the drain terminal and the source terminal (V
DS
) must be increased as V
GS
is being reduced in order to keep the current at a predefined level. This forces the FET to enter saturation region, which is a high power-operating region. Since the device is operating in a high power region in the current limiting mode, the junction temperature of the device will rise above allowable device limits and will cause damage to the FET unless thermal protection is implemented in the circuit. In order to prevent damage to the FET, a thermal protection circuit may be used to shut down or turn off the FET when the temperature exceeds a predefined level. Such a thermal protection circuit may be designed to turn the FET back on as the device temperature falls below a predefined level.
SUMMARY OF THE INVENTION
Accordingly, what is needed is a power FET switching circuit that will overcome the disadvantages of traditional fold-back current limiting methods. More specifically, what are needed are a circuit and/or method that will ensure that the operation of a power FET switch is always below its maximum operating limits. In addition, what are also needed are a circuit and/or method that will eliminate the need for temperature sensing or thermal shutdown circuits. The present invention provides these advantages and others not specifically mentioned above but described in the sections to follow.
What are described are a power FET and a replica FET on a semiconductor chip coupled to a logic control circuit on a second semiconductor chip within a single housing. A power FET and a scaled down replica of the power FET are disposed on a semiconductor chip. The power FET is used as a switch to couple a DC power source to a load. A fraction of the power FET drain current passes through the replica FET and an external sense resistor. When the voltage across the external sense resistor exceeds a maximum value based upon the maximum allowable power FET drain current, the logic control circuit enters into a pulsed gate (PG) mode of operation. The first step in the PG mode is to switch both FETs into a nonconducting state for a predefined period of time. After this time period, a ramp voltage applied between gate and source of both FETs switches them back into a current conducting state while holding the power FET drain current below its upper limit in the presence of a high capacitance or short circuit load. If the voltage across the external resistance increases above the maximum, the PG mode of operation continues. PG mode ceases and normal operation follows when the external resistance voltage remains below the established maximum. The combination of predefined non-conducting time and maximum drain current ensures operation of the power FET below maximum power dissipation limits. In other words, embodiments of the present invention keep the FET from operating in the saturation region. The PG mode of operation eliminates the need for additional temperature and thermal control circuits.
In one embodiment of the present invention, a power MOSFET and a replica of the power MOSFET disposed on a first semiconductor chip, and a logic and control circuit disposed on a second semiconductor chip are coupled and contained within a single housing. This semiconductor switching circuit utilizes negative feedback in order to maintain a drain current in the replica MOSFET that is a constant fractional value of the drain current in the power MOSFET. The replica MOSFET drain current is conducted through an external resistance. The value of the external resistance is selected in terms of the maximum allowable power MOSFET drain current in order to establish a trip.voltage level. A voltage across the external resistance greater than the trip voltage level will cause the logic and control circuit to enter a pulse gate (PG) mode of operation. In PG mode, both MOSFETs are initially switched into and held in a non-current conducting state for a period of time. At the end of this time period, a ramp voltage is applied gate-to-source to switch both MOSFETs in a timely manner back into a current conducting state. The ramp voltage ensures the MOSFETs do not exceed maximum current limits even in the presence of an excessive capacitive load. If the voltage across the external resistance exceeds the trip voltage level as the ramp voltage is applied, both MOSFETs will again be switched off and PG mode operation will repeat. Normal operation will then be established when power MOSFET drain current is reduced and the voltage across the external resistance remains below the trip voltage level. The combination of off time and maximum power MOSFET drain current established in the PG mode thus ensures operation of the power MOSFET below maximum power dissipation limits as established according to the thermal characteristics of the package used to house the devices. Furthermore, the need for any additional temperature sensing and/or thermal control circuits are eliminated.
In another embodiment of the present invention, a power MOSFET, a second MOSFET that is a reduced scale replica of the power MOSFET, and a logic and control circuit are coupled and contained within a common housing. The drain current in the second MOSFET is a fraction of the power MOSFET drain current. The logic circuit is capable of comparing the second MOSFET drain current with a presettable maximum value and switching both MOSFETs into a current blocking state whenever the second MOSFET drain current exceeds the presettable maximum. The circuit enters a pulse gate modulation (PG) mode where initially both MOSFETs are switched into and held in a current blocking state for a period of time. At the end of this time period, a ramp voltage is applied gate-to-source to switch both MOSFETs back into a current conducting state in a timely fashion. The ramp voltage ensures the MOSFETs do not exceed maximum current limits even in the presence of a large capacitive load. If the second MOSFET drain current exceeds the presettable maximum during ramp voltage application, both MOSFETs will again be switched off and PG mode of operation will repeat. Normal operation will then ensue when drain current remains below the presettable maximum. The combination of off time and maximum power MOSFET drain current established in the PG mode thus ensures operation of the power MOSFET below maximum power dissipation limits. Furthermore, in the present embodiment, the logic and control circuit will switch both MOSFETs into a current blocking state whenever the input power source voltage falls below a predetermined and settable value.
Another embodiment of the present invention limits the drain current in a hybrid power MOSFET circuit by using negative feedback to stabilize the ratio of power MOSFET drain current to a scaled replica MOSFET drain current, establishing an upper limit on the replica MOSFET drain current in terms of the upper limit on the power MOSFET drain current, and switching both MOSFETs into a non-conducting state whenever the upper limit on the replica MOSFET drain current is exceeded. The circuit enters a pulse gate modulation (PG) mode where both MOSFETs are initially switched into and held in a non-current conducting state for a period of time. At the end of the time period, a ramp voltage developed by a voltage doubler circuit is applied gate-to-source to switch both MOSFETs back into a current conducting state in a short tim

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